On Thu, Sep 06, 2012 at 01:00:02PM +0200, Michel Dänzer wrote:
> From: Michel Dänzer <michel.daen...@amd.com>
>
Reviewed-by: Tom Stellard <thomas.stell...@amd.com>
> Signed-off-by: Michel Dänzer <michel.daen...@amd.com>
> ---
> src/gallium/drivers/radeon/SIISelLowering.cpp | 13 +++++++++++++
> src/gallium/drivers/radeon/SIISelLowering.h | 2 ++
> src/gallium/drivers/radeon/SIInstructions.td | 7 +++++++
> src/gallium/drivers/radeon/SIIntrinsics.td | 1 +
> 4 files changed, 23 insertions(+)
>
> diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp
> b/src/gallium/drivers/radeon/SIISelLowering.cpp
> index 2c81673..ebe9514 100644
> --- a/src/gallium/drivers/radeon/SIISelLowering.cpp
> +++ b/src/gallium/drivers/radeon/SIISelLowering.cpp
> @@ -132,6 +132,9 @@ MachineBasicBlock *
> SITargetLowering::EmitInstrWithCustomInserter(
> case AMDGPU::SI_KIL:
> LowerSI_KIL(MI, *BB, I, MRI);
> break;
> + case AMDGPU::SI_WQM:
> + LowerSI_WQM(MI, *BB, I, MRI);
> + break;
> case AMDGPU::SI_V_CNDLT:
> LowerSI_V_CNDLT(MI, *BB, I, MRI);
> break;
> @@ -146,6 +149,16 @@ void SITargetLowering::AppendS_WAITCNT(MachineInstr *MI,
> MachineBasicBlock &BB,
> .addImm(0);
> }
>
> +
> +void SITargetLowering::LowerSI_WQM(MachineInstr *MI, MachineBasicBlock &BB,
> + MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const
> +{
> + BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WQM_B64),
> AMDGPU::EXEC)
> + .addReg(AMDGPU::EXEC);
> +
> + MI->eraseFromParent();
> +}
> +
> void SITargetLowering::LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock
> &BB,
> MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const
> {
> diff --git a/src/gallium/drivers/radeon/SIISelLowering.h
> b/src/gallium/drivers/radeon/SIISelLowering.h
> index 80c7f4b..4407bf0 100644
> --- a/src/gallium/drivers/radeon/SIISelLowering.h
> +++ b/src/gallium/drivers/radeon/SIISelLowering.h
> @@ -37,6 +37,8 @@ class SITargetLowering : public AMDGPUTargetLowering
> MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const;
> void LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB,
> MachineBasicBlock::iterator I, MachineRegisterInfo & MRI)
> const;
> + void LowerSI_WQM(MachineInstr *MI, MachineBasicBlock &BB,
> + MachineBasicBlock::iterator I, MachineRegisterInfo & MRI)
> const;
> void LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
> MachineBasicBlock::iterator I, MachineRegisterInfo & MRI)
> const;
>
> diff --git a/src/gallium/drivers/radeon/SIInstructions.td
> b/src/gallium/drivers/radeon/SIInstructions.td
> index 20d4c00..2868196 100644
> --- a/src/gallium/drivers/radeon/SIInstructions.td
> +++ b/src/gallium/drivers/radeon/SIInstructions.td
> @@ -986,6 +986,13 @@ def SI_KIL : InstSI <
> [(int_AMDGPU_kill VReg_32:$src)]
> >;
>
> +def SI_WQM : InstSI <
> + (outs),
> + (ins),
> + "SI_WQM",
> + [(int_SI_wqm)]
> +>;
> +
> } // end usesCustomInserter
>
> // SI Psuedo branch instructions. These are used by the CFG structurizer
> pass
> diff --git a/src/gallium/drivers/radeon/SIIntrinsics.td
> b/src/gallium/drivers/radeon/SIIntrinsics.td
> index 401325b..fbb8dc9 100644
> --- a/src/gallium/drivers/radeon/SIIntrinsics.td
> +++ b/src/gallium/drivers/radeon/SIIntrinsics.td
> @@ -20,6 +20,7 @@ let TargetPrefix = "SI", isTarget = 1 in {
> def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_i64_ty,
> llvm_i32_ty], []>;
> def int_SI_vs_load_buffer_index : Intrinsic <[llvm_i32_ty], [],
> [IntrNoMem]>;
> def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_v4i32_ty,
> llvm_i16_ty, llvm_i32_ty], []> ;
> + def int_SI_wqm : Intrinsic <[], [], []>;
>
> def int_SI_sample : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty,
> llvm_v4f32_ty, llvm_v8i32_ty, llvm_v4i32_ty]>;
>
> --
> 1.7.10.4
>
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