On Thu, Sep 06, 2012 at 01:00:00PM +0200, Michel Dänzer wrote:
> From: Michel Dänzer <michel.daen...@amd.com>
>
> Add 32 bit lo and hi variants, and binary encodings.
>
> Signed-off-by: Michel Dänzer <michel.daen...@amd.com>
> ---
> src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp | 3 +++
> src/gallium/drivers/radeon/SIGenRegisterInfo.pl | 4 +++-
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
> b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
> index c2b5e47..438d2ac 100644
> --- a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
> +++ b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
> @@ -281,6 +281,9 @@ unsigned SIMCCodeEmitter::getEncodingBytes(const MCInst
> &MI) const {
> unsigned SIMCCodeEmitter::getRegBinaryCode(unsigned reg) const {
> switch (reg) {
> case AMDGPU::M0: return 124;
> + case AMDGPU::EXEC: return 126;
> + case AMDGPU::EXEC_LO: return 126;
> + case AMDGPU::EXEC_HI: return 127;
> case AMDGPU::SREG_LIT_0: return 128;
> case AMDGPU::SI_LITERAL_CONSTANT: return 255;
> default: return getHWRegNum(reg);
> diff --git a/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
> b/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
> index e47fb56..9f8ca52 100644
> --- a/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
> +++ b/src/gallium/drivers/radeon/SIGenRegisterInfo.pl
> @@ -89,6 +89,8 @@ class SGPR_256 <bits<8> num, string name, list<Register>
> subregs> :
>
> def VCC : SIReg<"VCC">;
> def EXEC : SIReg<"EXEC">;
> +def EXEC_LO : SIReg<"EXEC LO">;
> +def EXEC_HI : SIReg<"EXEC HI">;
We need to tell the compiler that EXEC overlaps EXEC_LO and EXEC_HI, so
the EXEC definition should be changed to subclass SI_64, and EXEC_LO and
EXEC_HI should be passed to the constructor as sub-registers.
-Tom
> def SCC : SIReg<"SCC">;
> def SREG_LIT_0 : SIReg <"S LIT 0">;
> def SI_LITERAL_CONSTANT : SIReg<"LITERAL CONSTANT">;
> @@ -141,7 +143,7 @@ for (my $i = 0; $i < $VGPR_COUNT; $i++) {
> print <<STRING;
>
> def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
> - (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX), SREG_LIT_0, M0)
> + (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX), SREG_LIT_0, M0, EXEC_LO,
> EXEC_HI)
> >;
>
> def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
> --
> 1.7.10.4
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
