When rendering to an IMS MSAA surface on Gen7, blorp sets up the
rendering pipeline as though it were rendering to a single-sampled
surface; accordingly it must adjust the size of the primitive it sends
down the pipeline to account for the interleaving of samples in an IMS
surface.
This patch modifies the size adjustment code to properly handle 8x
MSAA, which makes room for the extra samples by using an interleaving
pattern that is twice as wide as 4x MSAA.
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 21 +++++++++++++++++----
1 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index f750d42..940a293 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -1632,10 +1632,23 @@ brw_blorp_blit_params::brw_blorp_blit_params(struct
brw_context *brw,
* pipeline as multisampled.
*/
assert(dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS);
- x0 = (x0 * 2) & ~3;
- y0 = (y0 * 2) & ~3;
- x1 = ALIGN(x1 * 2, 4);
- y1 = ALIGN(y1 * 2, 4);
+ switch (dst_mt->num_samples) {
+ case 4:
+ x0 = (x0 * 2) & ~3;
+ y0 = (y0 * 2) & ~3;
+ x1 = ALIGN(x1 * 2, 4);
+ y1 = ALIGN(y1 * 2, 4);
+ break;
+ case 8:
+ x0 = (x0 * 4) & ~7;
+ y0 = (y0 * 2) & ~3;
+ x1 = ALIGN(x1 * 4, 8);
+ y1 = ALIGN(y1 * 2, 4);
+ break;
+ default:
+ assert(!"Unrecognized sample count in brw_blorp_blit_params ctor");
+ break;
+ }
wm_prog_key.use_kill = true;
}
--
1.7.7.6
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