On 05/10/2012 11:21 AM, Paul Berry wrote: > This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to > understand multisampled buffers, adapting the rendering pipeline setup > to enable multisampled rendering, and adding multisample resolve > operations to brw_blorp_blit.cpp. Some preparation work is also > included for Gen7, but it is not yet enabled. > > MSAA support is still fairly preliminary. In particular, the > following are not yet supported: > - Fully general blits between MSAA and non-MSAA buffers. > - Formats other than RGBA8, DEPTH24, and STENCIL8. > - Centroid interpolation. > - Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE, > GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE, > GL_SAMPLE_COVERAGE_INVERT). > > Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on > i965/Gen6. > > v2: > - In intel_alloc_renderbuffer_storage(), quantize the requested number > of samples to the next higher sample count supported by the > hardware. This ensures that a query of GL_SAMPLES will return the > correct value. It also ensures that MSAA is fully disabled on Gen7 > for now (since Gen7 MSAA support doesn't work yet). > - When reading from a non-MSAA surface, ensure that s_is_zero is true > so that we won't try to read from a nonexistent sample. > --- > src/mesa/drivers/dri/i965/Makefile.sources | 1 + > src/mesa/drivers/dri/i965/brw_blorp.cpp | 10 +- > src/mesa/drivers/dri/i965/brw_blorp.h | 30 ++- > src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 332 > +++++++++++++++++--- > src/mesa/drivers/dri/i965/brw_context.h | 8 + > src/mesa/drivers/dri/i965/brw_defines.h | 7 + > src/mesa/drivers/dri/i965/brw_misc_state.c | 33 +-- > src/mesa/drivers/dri/i965/brw_state.h | 4 + > src/mesa/drivers/dri/i965/brw_state_upload.c | 2 + > src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16 +- > src/mesa/drivers/dri/i965/gen6_blorp.cpp | 44 ++-- > src/mesa/drivers/dri/i965/gen6_multisample_state.c | 102 ++++++ > src/mesa/drivers/dri/i965/gen6_sf_state.c | 15 +- > src/mesa/drivers/dri/i965/gen6_wm_state.c | 12 + > src/mesa/drivers/dri/i965/gen7_blorp.cpp | 20 +- > src/mesa/drivers/dri/i965/gen7_sf_state.c | 14 +- > src/mesa/drivers/dri/i965/gen7_wm_state.c | 18 +- > src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 16 + > src/mesa/drivers/dri/intel/intel_fbo.c | 31 ++- > src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 52 +++- > src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 10 +- > src/mesa/drivers/dri/intel/intel_tex_image.c | 3 +- > src/mesa/drivers/dri/intel/intel_tex_validate.c | 3 +- > 23 files changed, 662 insertions(+), 121 deletions(-) > create mode 100644 src/mesa/drivers/dri/i965/gen6_multisample_state.c
I tried reviewing this one, but the patch does so much at once that I quickly got lost. And, anyway, I don't understand brw shaders. Do you intend to push this today regardless of receiving review? I see that you have gen7 patches queued up dependent on this series. ---- Chad Versace chad.vers...@linux.intel.com _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
