From: Marek Olšák <marek.ol...@amd.com>
Window system buffers didn't use the optimal alignment.
---
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 49 ++++++++++++++---------
1 file changed, 29 insertions(+), 20 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index d9cfef315ca..7b239695872 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -385,20 +385,41 @@ static void amdgpu_add_buffer_to_global_list(struct
amdgpu_winsys_bo *bo)
assert(bo->bo);
if (ws->debug_all_bos) {
simple_mtx_lock(&ws->global_bo_list_lock);
LIST_ADDTAIL(&bo->u.real.global_list_item, &ws->global_bo_list);
ws->num_buffers++;
simple_mtx_unlock(&ws->global_bo_list_lock);
}
}
+static uint64_t amdgpu_get_optimal_vm_alignment(struct amdgpu_winsys *ws,
+ uint64_t size, unsigned
alignment)
+{
+ uint64_t vm_alignment = alignment;
+
+ /* Increase the VM alignment for faster address translation. */
+ if (size >= ws->info.pte_fragment_size)
+ vm_alignment = MAX2(vm_alignment, ws->info.pte_fragment_size);
+
+ /* Gfx9: Increase the VM alignment to the most significant bit set
+ * in the size for faster address translation.
+ */
+ if (ws->info.chip_class >= GFX9) {
+ unsigned msb = util_last_bit64(size); /* 0 = no bit is set */
+ uint64_t msb_alignment = msb ? 1ull << (msb - 1) : 0;
+
+ vm_alignment = MAX2(vm_alignment, msb_alignment);
+ }
+ return vm_alignment;
+}
+
static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws,
uint64_t size,
unsigned alignment,
enum radeon_bo_domain
initial_domain,
unsigned flags,
int heap)
{
struct amdgpu_bo_alloc_request request = {0};
amdgpu_bo_handle buf_handle;
uint64_t va = 0;
@@ -474,40 +495,26 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct
amdgpu_winsys *ws,
if (r) {
fprintf(stderr, "amdgpu: Failed to allocate a buffer:\n");
fprintf(stderr, "amdgpu: size : %"PRIu64" bytes\n", size);
fprintf(stderr, "amdgpu: alignment : %u bytes\n", alignment);
fprintf(stderr, "amdgpu: domains : %u\n", initial_domain);
goto error_bo_alloc;
}
va_gap_size = ws->check_vm ? MAX2(4 * alignment, 64 * 1024) : 0;
- uint64_t vm_alignment = alignment;
-
- /* Increase the VM alignment for faster address translation. */
- if (size >= ws->info.pte_fragment_size)
- vm_alignment = MAX2(vm_alignment, ws->info.pte_fragment_size);
-
- /* Gfx9: Increase the VM alignment to the most significant bit set
- * in the size for faster address translation.
- */
- if (ws->info.chip_class >= GFX9) {
- unsigned msb = util_last_bit64(size); /* 0 = no bit is set */
- uint64_t msb_alignment = msb ? 1ull << (msb - 1) : 0;
-
- vm_alignment = MAX2(vm_alignment, msb_alignment);
- }
-
r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
- size + va_gap_size, vm_alignment, 0, &va,
&va_handle,
+ size + va_gap_size,
+ amdgpu_get_optimal_vm_alignment(ws, size,
alignment),
+ 0, &va, &va_handle,
(flags & RADEON_FLAG_32BIT ?
AMDGPU_VA_RANGE_32_BIT : 0) |
- AMDGPU_VA_RANGE_HIGH);
+ AMDGPU_VA_RANGE_HIGH);
if (r)
goto error_va_alloc;
unsigned vm_flags = AMDGPU_VM_PAGE_READABLE |
AMDGPU_VM_PAGE_EXECUTABLE;
if (!(flags & RADEON_FLAG_READ_ONLY))
vm_flags |= AMDGPU_VM_PAGE_WRITEABLE;
r = amdgpu_bo_va_op_raw(ws->dev, buf_handle, 0, size, va, vm_flags,
@@ -1412,22 +1419,24 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct
radeon_winsys *rws,
amdgpu_bo_free(result.buf_handle);
return &bo->base;
}
/* Get initial domains. */
r = amdgpu_bo_query_info(result.buf_handle, &info);
if (r)
goto error;
r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
- result.alloc_size, vm_alignment, 0, &va,
&va_handle,
- AMDGPU_VA_RANGE_HIGH);
+ result.alloc_size,
+ amdgpu_get_optimal_vm_alignment(ws,
result.alloc_size,
+ vm_alignment),
+ 0, &va, &va_handle, AMDGPU_VA_RANGE_HIGH);
if (r)
goto error;
bo = CALLOC_STRUCT(amdgpu_winsys_bo);
if (!bo)
goto error;
r = amdgpu_bo_va_op(result.buf_handle, 0, result.alloc_size, va, 0,
AMDGPU_VA_OP_MAP);
if (r)
goto error;
--
2.17.1
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