From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/r300/r300_texture.c | 2 +-
src/gallium/drivers/r600/r600_texture.c | 5 ++++-
src/gallium/drivers/radeon/radeon_winsys.h | 1 +
src/gallium/drivers/radeonsi/si_texture.c | 5 ++++-
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 3 ++-
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 3 ++-
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 1 +
7 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_texture.c
b/src/gallium/drivers/r300/r300_texture.c
index 6f8893eee6c..46d88b34638 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -1175,21 +1175,21 @@ struct pipe_resource *r300_texture_from_handle(struct
pipe_screen *screen,
struct radeon_bo_metadata tiling = {};
/* Support only 2D textures without mipmaps */
if ((base->target != PIPE_TEXTURE_2D &&
base->target != PIPE_TEXTURE_RECT) ||
base->depth0 != 1 ||
base->last_level != 0) {
return NULL;
}
- buffer = rws->buffer_from_handle(rws, whandle, &stride, NULL);
+ buffer = rws->buffer_from_handle(rws, whandle, 0, &stride, NULL);
if (!buffer)
return NULL;
rws->buffer_get_metadata(buffer, &tiling);
/* Enforce a microtiled zbuffer. */
if (util_format_is_depth_or_stencil(base->format) &&
tiling.u.legacy.microtile == RADEON_LAYOUT_LINEAR) {
switch (util_format_get_blocksize(base->format)) {
case 4:
diff --git a/src/gallium/drivers/r600/r600_texture.c
b/src/gallium/drivers/r600/r600_texture.c
index def4cbf86b2..71606df38d9 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -1101,21 +1101,23 @@ static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen *screen
int r;
struct radeon_bo_metadata metadata = {};
struct r600_texture *rtex;
bool is_scanout;
/* Support only 2D textures without mipmaps */
if ((templ->target != PIPE_TEXTURE_2D && templ->target !=
PIPE_TEXTURE_RECT) ||
templ->depth0 != 1 || templ->last_level != 0)
return NULL;
- buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride,
&offset);
+ buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
+ rscreen->info.max_alignment,
+ &stride, &offset);
if (!buf)
return NULL;
rscreen->ws->buffer_get_metadata(buf, &metadata);
r600_surface_import_metadata(rscreen, &surface, &metadata,
&array_mode, &is_scanout);
r = r600_init_surface(rscreen, &surface, templ, array_mode, stride,
offset, true, is_scanout, false);
if (r) {
@@ -1845,20 +1847,21 @@ r600_memobj_from_handle(struct pipe_screen *screen,
{
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
struct r600_memory_object *memobj = CALLOC_STRUCT(r600_memory_object);
struct pb_buffer *buf = NULL;
uint32_t stride, offset;
if (!memobj)
return NULL;
buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
+ rscreen->info.max_alignment,
&stride, &offset);
if (!buf) {
free(memobj);
return NULL;
}
memobj->b.dedicated = dedicated;
memobj->buf = buf;
memobj->stride = stride;
memobj->offset = offset;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index 49f8bb279e5..3d0bb75ef6e 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -345,20 +345,21 @@ struct radeon_winsys {
* Get a winsys buffer from a winsys handle. The internal structure
* of the handle is platform-specific and only a winsys should access it.
*
* \param ws The winsys this function is called from.
* \param whandle A winsys handle pointer as was received from a state
* tracker.
* \param stride The returned buffer stride in bytes.
*/
struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws,
struct winsys_handle *whandle,
+ unsigned vm_alignment,
unsigned *stride, unsigned
*offset);
/**
* Get a winsys buffer from a user pointer. The resulting buffer can't
* be exported. Both pointer and size must be page aligned.
*
* \param ws The winsys this function is called from.
* \param pointer User pointer to turn into a buffer object.
* \param Size Size in bytes for the new buffer.
*/
diff --git a/src/gallium/drivers/radeonsi/si_texture.c
b/src/gallium/drivers/radeonsi/si_texture.c
index 2fb79253a72..95f1e8c9693 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -1480,21 +1480,23 @@ static struct pipe_resource
*si_texture_from_handle(struct pipe_screen *screen,
{
struct si_screen *sscreen = (struct si_screen*)screen;
struct pb_buffer *buf = NULL;
unsigned stride = 0, offset = 0;
/* Support only 2D textures without mipmaps */
if ((templ->target != PIPE_TEXTURE_2D && templ->target !=
PIPE_TEXTURE_RECT) ||
templ->depth0 != 1 || templ->last_level != 0)
return NULL;
- buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, &stride,
&offset);
+ buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle,
+ sscreen->info.max_alignment,
+ &stride, &offset);
if (!buf)
return NULL;
return si_texture_from_winsys_buffer(sscreen, templ, buf, stride,
offset, usage, true);
}
bool si_init_flushed_depth_texture(struct pipe_context *ctx,
struct pipe_resource *texture,
struct si_texture **staging)
@@ -2331,20 +2333,21 @@ si_memobj_from_handle(struct pipe_screen *screen,
{
struct si_screen *sscreen = (struct si_screen*)screen;
struct si_memory_object *memobj = CALLOC_STRUCT(si_memory_object);
struct pb_buffer *buf = NULL;
uint32_t stride, offset;
if (!memobj)
return NULL;
buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle,
+ sscreen->info.max_alignment,
&stride, &offset);
if (!buf) {
free(memobj);
return NULL;
}
memobj->b.dedicated = dedicated;
memobj->buf = buf;
memobj->stride = stride;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 5139e765b72..d9cfef315ca 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -1354,20 +1354,21 @@ no_slab:
if (!bo)
return NULL;
}
bo->u.real.use_reusable_pool = use_reusable_pool;
return &bo->base;
}
static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws,
struct winsys_handle *whandle,
+ unsigned vm_alignment,
unsigned *stride,
unsigned *offset)
{
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_winsys_bo *bo = NULL;
enum amdgpu_bo_handle_type type;
struct amdgpu_bo_import_result result = {0};
uint64_t va;
amdgpu_va_handle va_handle = NULL;
struct amdgpu_bo_info info = {0};
@@ -1411,21 +1412,21 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct
radeon_winsys *rws,
amdgpu_bo_free(result.buf_handle);
return &bo->base;
}
/* Get initial domains. */
r = amdgpu_bo_query_info(result.buf_handle, &info);
if (r)
goto error;
r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
- result.alloc_size, 1 << 20, 0, &va, &va_handle,
+ result.alloc_size, vm_alignment, 0, &va,
&va_handle,
AMDGPU_VA_RANGE_HIGH);
if (r)
goto error;
bo = CALLOC_STRUCT(amdgpu_winsys_bo);
if (!bo)
goto error;
r = amdgpu_bo_va_op(result.buf_handle, 0, result.alloc_size, va, 0,
AMDGPU_VA_OP_MAP);
if (r)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 07a9b2d758e..d1e2a8685ba 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -1127,20 +1127,21 @@ static struct pb_buffer
*radeon_winsys_bo_from_ptr(struct radeon_winsys *rws,
mtx_unlock(&ws->bo_handles_mutex);
}
ws->allocated_gtt += align(bo->base.size, ws->info.gart_page_size);
return (struct pb_buffer*)bo;
}
static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys
*rws,
struct winsys_handle
*whandle,
+ unsigned vm_alignment,
unsigned *stride,
unsigned *offset)
{
struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
struct radeon_bo *bo;
int r;
unsigned handle;
uint64_t size = 0;
if (!offset && whandle->offset != 0) {
@@ -1232,21 +1233,21 @@ done:
mtx_unlock(&ws->bo_handles_mutex);
if (stride)
*stride = whandle->stride;
if (offset)
*offset = whandle->offset;
if (ws->info.r600_has_virtual_memory && !bo->va) {
struct drm_radeon_gem_va va;
- bo->va = radeon_bomgr_find_va64(ws, bo->base.size, 1 << 20);
+ bo->va = radeon_bomgr_find_va64(ws, bo->base.size, vm_alignment);
va.handle = bo->handle;
va.operation = RADEON_VA_MAP;
va.vm_id = 0;
va.offset = bo->va;
va.flags = RADEON_VM_PAGE_READABLE |
RADEON_VM_PAGE_WRITEABLE |
RADEON_VM_PAGE_SNOOPED;
va.offset = bo->va;
r = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_VA, &va, sizeof(va));
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index cf07a8d8e26..293372cc26d 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -582,20 +582,21 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.has_indirect_compute_dispatch = ws->info.chip_class == CIK ||
(ws->info.chip_class == SI &&
ws->info.drm_minor >= 45);
/* SI doesn't support unaligned loads. */
ws->info.has_unaligned_shader_loads = ws->info.chip_class == CIK &&
ws->info.drm_minor >= 50;
ws->info.has_sparse_vm_mappings = false;
/* 2D tiling on CIK is supported since DRM 2.35.0 */
ws->info.has_2d_tiling = ws->info.chip_class <= SI || ws->info.drm_minor
>= 35;
ws->info.has_read_registers_query = ws->info.drm_minor >= 42;
+ ws->info.max_alignment = 1024*1024;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") !=
NULL;
return true;
}
static void radeon_winsys_destroy(struct radeon_winsys *rws)
{
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
--
2.17.1
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