---
src/intel/compiler/brw_eu_emit.c | 4 ++--
src/intel/compiler/brw_fs.cpp | 2 +-
src/intel/compiler/brw_fs_generator.cpp | 2 +-
src/intel/compiler/brw_fs_reg_allocate.cpp | 4 ++--
src/intel/compiler/brw_ir_fs.h | 4 ++--
src/mesa/drivers/dri/i965/brw_clip.c | 2 +-
src/mesa/drivers/dri/i965/brw_vs.c | 2 +-
src/mesa/drivers/dri/radeon/radeon_texture.c | 2 +-
src/mesa/main/imports.h | 20 --------------------
src/mesa/main/teximage.c | 12 ++++++------
src/mesa/state_tracker/st_cb_texture.c | 2 +-
11 files changed, 18 insertions(+), 38 deletions(-)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 4630b83b1a0..fe497f6dfc3 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -505,7 +505,7 @@ gen7_set_dp_scratch_message(struct brw_codegen *p,
const struct gen_device_info *devinfo = p->devinfo;
assert(num_regs == 1 || num_regs == 2 || num_regs == 4 ||
(devinfo->gen >= 8 && num_regs == 8));
- const unsigned block_size = (devinfo->gen >= 8 ? _mesa_logbase2(num_regs) :
+ const unsigned block_size = (devinfo->gen >= 8 ? util_logbase2(num_regs) :
num_regs - 1);
brw_set_desc(p, inst, brw_message_desc(
@@ -3455,7 +3455,7 @@ brw_broadcast(struct brw_codegen *p,
/* Take into account the component size and horizontal stride. */
assert(src.vstride == src.hstride + src.width);
brw_SHL(p, addr, vec1(idx),
- brw_imm_ud(_mesa_logbase2(type_sz(src.type)) +
+ brw_imm_ud(util_logbase2(type_sz(src.type)) +
src.hstride - 1));
/* We can only address up to limit bytes using the indirect
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 3e083723471..1ae97578190 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -5241,7 +5241,7 @@ get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo,
/* Only power-of-two execution sizes are representable in the instruction
* control fields.
*/
- return 1 << _mesa_logbase2(max_width);
+ return 1 << util_logbase2(max_width);
}
/**
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index 08dd83dded7..a3d22642887 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -542,7 +542,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
/* Take into account the component size and horizontal stride. */
assert(src.vstride == src.hstride + src.width);
brw_SHL(p, addr, group_idx,
- brw_imm_uw(_mesa_logbase2(type_sz(src.type)) +
+ brw_imm_uw(util_logbase2(type_sz(src.type)) +
src.hstride - 1));
/* Add on the register start offset */
diff --git a/src/intel/compiler/brw_fs_reg_allocate.cpp
b/src/intel/compiler/brw_fs_reg_allocate.cpp
index 73b8b7841f5..bbb629752e2 100644
--- a/src/intel/compiler/brw_fs_reg_allocate.cpp
+++ b/src/intel/compiler/brw_fs_reg_allocate.cpp
@@ -77,7 +77,7 @@ brw_alloc_reg_set(struct brw_compiler *compiler, int
dispatch_width)
{
const struct gen_device_info *devinfo = compiler->devinfo;
int base_reg_count = BRW_MAX_GRF;
- const int index = _mesa_logbase2(dispatch_width / 8);
+ const int index = util_logbase2(dispatch_width / 8);
if (dispatch_width > 8 && devinfo->gen >= 7) {
/* For IVB+, we don't need the PLN hacks or the even-reg alignment in
@@ -539,7 +539,7 @@ fs_visitor::assign_regs(bool allow_spilling, bool spill_all)
int reg_width = dispatch_width / 8;
unsigned hw_reg_mapping[this->alloc.count];
int payload_node_count = ALIGN(this->first_non_payload_grf, reg_width);
- int rsi = _mesa_logbase2(reg_width); /* Which compiler->fs_reg_sets[] to
use */
+ int rsi = util_logbase2(reg_width); /* Which compiler->fs_reg_sets[] to use
*/
calculate_live_intervals();
int node_count = this->alloc.count;
diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h
index 07e7224e0f8..599aea74153 100644
--- a/src/intel/compiler/brw_ir_fs.h
+++ b/src/intel/compiler/brw_ir_fs.h
@@ -298,8 +298,8 @@ subscript(fs_reg reg, brw_reg_type type, unsigned i)
/* The stride is encoded inconsistently for fixed GRF and ARF registers
* as the log2 of the actual vertical and horizontal strides.
*/
- const int delta = _mesa_logbase2(type_sz(reg.type)) -
- _mesa_logbase2(type_sz(type));
+ const int delta = util_logbase2(type_sz(reg.type)) -
+ util_logbase2(type_sz(type));
reg.hstride += (reg.hstride ? delta : 0);
reg.vstride += (reg.vstride ? delta : 0);
diff --git a/src/mesa/drivers/dri/i965/brw_clip.c
b/src/mesa/drivers/dri/i965/brw_clip.c
index 49c41d8c2e4..082724c82d1 100644
--- a/src/mesa/drivers/dri/i965/brw_clip.c
+++ b/src/mesa/drivers/dri/i965/brw_clip.c
@@ -112,7 +112,7 @@ brw_upload_clip_prog(struct brw_context *brw)
key.pv_first = (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION);
/* _NEW_TRANSFORM (also part of VUE map)*/
if (ctx->Transform.ClipPlanesEnabled)
- key.nr_userclip = _mesa_logbase2(ctx->Transform.ClipPlanesEnabled) + 1;
+ key.nr_userclip = util_logbase2(ctx->Transform.ClipPlanesEnabled) + 1;
if (devinfo->gen == 5)
key.clip_mode = BRW_CLIP_MODE_KERNEL_CLIP;
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
b/src/mesa/drivers/dri/i965/brw_vs.c
index 69c0046bbb9..b4d5b82adf0 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -297,7 +297,7 @@ brw_vs_populate_key(struct brw_context *brw,
(ctx->API == API_OPENGL_COMPAT || ctx->API == API_OPENGLES) &&
vp->program.info.clip_distance_array_size == 0) {
key->nr_userclip_plane_consts =
- _mesa_logbase2(ctx->Transform.ClipPlanesEnabled) + 1;
+ util_logbase2(ctx->Transform.ClipPlanesEnabled) + 1;
}
if (devinfo->gen < 6) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c
b/src/mesa/drivers/dri/radeon/radeon_texture.c
index f2d435a375f..6639c7ed65e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -685,7 +685,7 @@ static radeon_mipmap_tree
*radeon_miptree_create_for_teximage(radeonContextPtr r
texImage->Level == firstLevel) {
lastLevel = firstLevel;
} else {
- lastLevel = firstLevel +
_mesa_logbase2(MAX2(MAX2(width, height), depth));
+ lastLevel = firstLevel + util_logbase2(MAX2(MAX2(width,
height), depth));
}
}
diff --git a/src/mesa/main/imports.h b/src/mesa/main/imports.h
index 3ed2c5edb07..863ac56f535 100644
--- a/src/mesa/main/imports.h
+++ b/src/mesa/main/imports.h
@@ -206,26 +206,6 @@ static inline int IFLOOR(float f)
}
-/*
- * Returns the floor form of binary logarithm for a 32-bit integer.
- */
-static inline GLuint
-_mesa_logbase2(GLuint n)
-{
-#ifdef HAVE___BUILTIN_CLZ
- return (31 - __builtin_clz(n | 1));
-#else
- GLuint pos = 0;
- if (n >= 1<<16) { n >>= 16; pos += 16; }
- if (n >= 1<< 8) { n >>= 8; pos += 8; }
- if (n >= 1<< 4) { n >>= 4; pos += 4; }
- if (n >= 1<< 2) { n >>= 2; pos += 2; }
- if (n >= 1<< 1) { pos += 1; }
- return pos;
-#endif
-}
-
-
/**
* Return 1 if this is a little endian machine, 0 if big endian.
*/
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 9ed31840868..ab1473653c5 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -736,7 +736,7 @@ _mesa_get_tex_max_num_levels(GLenum target, GLsizei width,
GLsizei height,
return 1;
}
- return _mesa_logbase2(size) + 1;
+ return util_logbase2(size) + 1;
}
@@ -862,7 +862,7 @@ _mesa_init_teximage_fields_ms(struct gl_context *ctx,
img->Depth = depth;
img->Width2 = width - 2 * border; /* == 1 << img->WidthLog2; */
- img->WidthLog2 = _mesa_logbase2(img->Width2);
+ img->WidthLog2 = util_logbase2(img->Width2);
switch(target) {
case GL_TEXTURE_1D:
@@ -905,7 +905,7 @@ _mesa_init_teximage_fields_ms(struct gl_context *ctx,
case GL_TEXTURE_2D_MULTISAMPLE:
case GL_PROXY_TEXTURE_2D_MULTISAMPLE:
img->Height2 = height - 2 * border; /* == 1 << img->HeightLog2; */
- img->HeightLog2 = _mesa_logbase2(img->Height2);
+ img->HeightLog2 = util_logbase2(img->Height2);
if (depth == 0)
img->Depth2 = 0;
else
@@ -919,16 +919,16 @@ _mesa_init_teximage_fields_ms(struct gl_context *ctx,
case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
case GL_PROXY_TEXTURE_2D_MULTISAMPLE_ARRAY:
img->Height2 = height - 2 * border; /* == 1 << img->HeightLog2; */
- img->HeightLog2 = _mesa_logbase2(img->Height2);
+ img->HeightLog2 = util_logbase2(img->Height2);
img->Depth2 = depth; /* no border */
img->DepthLog2 = 0; /* not used */
break;
case GL_TEXTURE_3D:
case GL_PROXY_TEXTURE_3D:
img->Height2 = height - 2 * border; /* == 1 << img->HeightLog2; */
- img->HeightLog2 = _mesa_logbase2(img->Height2);
+ img->HeightLog2 = util_logbase2(img->Height2);
img->Depth2 = depth - 2 * border; /* == 1 << img->DepthLog2; */
- img->DepthLog2 = _mesa_logbase2(img->Depth2);
+ img->DepthLog2 = util_logbase2(img->Depth2);
break;
default:
_mesa_problem(NULL, "invalid target 0x%x in
_mesa_init_teximage_fields()",
diff --git a/src/mesa/state_tracker/st_cb_texture.c
b/src/mesa/state_tracker/st_cb_texture.c
index b8cc616d8f2..01c1e625a38 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -2994,7 +2994,7 @@ st_TestProxyTexImage(struct gl_context *ctx, GLenum
target,
}
else {
/* assume a full set of mipmaps */
- pt.last_level = _mesa_logbase2(MAX3(width, height, depth));
+ pt.last_level = util_logbase2(MAX3(width, height, depth));
}
return pipe->screen->can_create_resource(pipe->screen, &pt);
--
2.19.1
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