Due to some idiosyncrasies of the dispatch logic on gen8+ hardware, we
have to manually force the fragment shader to actually be dispatched when a
shader has side effects or uses discard and color writes are disabled.

Historically, we have done this with 3DSTATE_PS::PixelShaderHasUAV which
enforces thread dispatch and also enables some additional coherency between
shader stages that's demanded by D3D.  Unfortunately, this occasionally
causes hangs on gen8 for unknown reasons.  About four months ago, we
stopped setting 3DSTATE_PS::PixelShaderHasUAV in favor of using the
3DSTATE_WM::ForceThreadDispatchEnable flag.  This solved the issue on
Broadwell but caused problems on Skylake.  Today, I pushed 0fa9e6d7b304f
which makes us use 3DSTATE_PS::PixelShaderHasUAV on Skylake and above and
3DSTATE_WM::ForceThreadDispatchEnable flag on Broadwell only.  This gets
rid of all known hangs but isn't a terribly satisfactory solution.

While searching through my inbox looking for this stuff today, I came
across this e-mail from Francisco:

https://lists.freedesktop.org/archives/mesa-dev/2017-February/144269.html

He suggested in that mail that setting ForceDispatchEnable may not be safe
because it forces WM thread dispatch even for HiZ ops where it is normally
disabled.  So today, I decided to give that a go (patch 1 below) and it
seems to fix the hangs we were seeing in Dota 2 on Skylake when using
3DSTATE_WM::ForceThreadDispatchEnable.  I suspect that this is the more
proper fix so I'd like to revert the fix which splits things across gens
and instead us 3DSTATE_WM::ForceThreadDispatchEnable everywhere and make
sure that it's set to normal for HiZ ops.

Cc: Kenneth Graunke <kenn...@whitecape.org>

Jason Ekstrand (2):
  blorp: Emit a dummy 3DSTATE_WM prior to 3DSTATE_WM_HZ_OP
  Revert "anv/skylake: disable ForceThreadDispatchEnable"

 src/intel/blorp/blorp_genX_exec.h |  9 +++++++
 src/intel/vulkan/genX_pipeline.c  | 42 ++++++-------------------------
 2 files changed, 16 insertions(+), 35 deletions(-)

-- 
2.19.1

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