From: Marek Olšák <marek.ol...@amd.com> According to: https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf
Also Intel: https://www.microbe.cz/docs/CPUID.pdf --- src/gallium/auxiliary/util/u_cpu_detect.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/util/u_cpu_detect.c b/src/gallium/auxiliary/util/u_cpu_detect.c index 93cf58011db..29f4ce98203 100644 --- a/src/gallium/auxiliary/util/u_cpu_detect.c +++ b/src/gallium/auxiliary/util/u_cpu_detect.c @@ -413,22 +413,23 @@ util_cpu_detect_once(void) /* Get max cpuid level */ cpuid(0x00000000, regs); if (regs[0] >= 0x00000001) { unsigned int cacheline; cpuid (0x00000001, regs2); util_cpu_caps.x86_cpu_type = (regs2[0] >> 8) & 0xf; + /* Add "extended family". */ if (util_cpu_caps.x86_cpu_type == 0xf) - util_cpu_caps.x86_cpu_type = 8 + ((regs2[0] >> 20) & 255); /* use extended family (P4, IA64) */ + util_cpu_caps.x86_cpu_type += ((regs2[0] >> 20) & 0xff); /* general feature flags */ util_cpu_caps.has_tsc = (regs2[3] >> 4) & 1; /* 0x0000010 */ util_cpu_caps.has_mmx = (regs2[3] >> 23) & 1; /* 0x0800000 */ util_cpu_caps.has_sse = (regs2[3] >> 25) & 1; /* 0x2000000 */ util_cpu_caps.has_sse2 = (regs2[3] >> 26) & 1; /* 0x4000000 */ util_cpu_caps.has_sse3 = (regs2[2] >> 0) & 1; /* 0x0000001 */ util_cpu_caps.has_ssse3 = (regs2[2] >> 9) & 1; /* 0x0000020 */ util_cpu_caps.has_sse4_1 = (regs2[2] >> 19) & 1; util_cpu_caps.has_sse4_2 = (regs2[2] >> 20) & 1; -- 2.17.1 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
