[Mesa-dev] [PATCH 3/8] gallium/u_cpu_detect: get the number of cores per L3 cache for AMD Zen

[Marek Olšák]

From: Marek Olšák <marek.ol...@amd.com>

---
 src/gallium/auxiliary/util/u_cpu_detect.c | 24 +++++++++++++++++++++++
 src/gallium/auxiliary/util/u_cpu_detect.h |  1 +
 2 files changed, 25 insertions(+)

diff --git a/src/gallium/auxiliary/util/u_cpu_detect.c 
b/src/gallium/auxiliary/util/u_cpu_detect.c
index 29f4ce98203..751443f06f9 100644
--- a/src/gallium/auxiliary/util/u_cpu_detect.c
+++ b/src/gallium/auxiliary/util/u_cpu_detect.c
@@ -360,20 +360,42 @@ check_os_arm_support(void)
              util_cpu_caps.has_neon = (hwcap >> 12) & 1;
              break;
           }
        }
        close (fd);
     }
 #endif /* PIPE_OS_LINUX */
 }
 #endif /* PIPE_ARCH_ARM */
 
+static void
+get_cpu_topology(void)
+{
+   uint32_t regs[4];
+
+   /* Default. This is correct if L3 is not present or there is only one. */
+   util_cpu_caps.cores_per_L3 = util_cpu_caps.nr_cpus;
+
+#if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
+   /* AMD Zen */
+   if (util_cpu_caps.x86_cpu_type == 0x17) {
+      /* Query the L3 cache topology information. */
+      cpuid_count(0x8000001D, 3, regs);
+      unsigned cache_level = (regs[0] >> 5) & 0x7;
+      unsigned cores_per_cache = ((regs[0] >> 14) & 0xfff) + 1;
+
+      if (cache_level == 3)
+         util_cpu_caps.cores_per_L3 = cores_per_cache;
+   }
+#endif
+}
+
 static void
 util_cpu_detect_once(void)
 {
    memset(&util_cpu_caps, 0, sizeof util_cpu_caps);
 
    /* Count the number of CPUs in system */
 #if defined(PIPE_OS_WINDOWS)
    {
       SYSTEM_INFO system_info;
       GetSystemInfo(&system_info);
@@ -513,20 +535,22 @@ util_cpu_detect_once(void)
 #endif /* PIPE_ARCH_X86 || PIPE_ARCH_X86_64 */
 
 #if defined(PIPE_ARCH_ARM)
    check_os_arm_support();
 #endif
 
 #if defined(PIPE_ARCH_PPC)
    check_os_altivec_support();
 #endif /* PIPE_ARCH_PPC */
 
+   get_cpu_topology();
+
 #ifdef DEBUG
    if (debug_get_option_dump_cpu()) {
       debug_printf("util_cpu_caps.nr_cpus = %u\n", util_cpu_caps.nr_cpus);
 
       debug_printf("util_cpu_caps.x86_cpu_type = %u\n", 
util_cpu_caps.x86_cpu_type);
       debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps.cacheline);
 
       debug_printf("util_cpu_caps.has_tsc = %u\n", util_cpu_caps.has_tsc);
       debug_printf("util_cpu_caps.has_mmx = %u\n", util_cpu_caps.has_mmx);
       debug_printf("util_cpu_caps.has_mmx2 = %u\n", util_cpu_caps.has_mmx2);
diff --git a/src/gallium/auxiliary/util/u_cpu_detect.h 
b/src/gallium/auxiliary/util/u_cpu_detect.h
index 19f5567ca7b..efc910d1473 100644
--- a/src/gallium/auxiliary/util/u_cpu_detect.h
+++ b/src/gallium/auxiliary/util/u_cpu_detect.h
@@ -44,20 +44,21 @@
 extern "C" {
 #endif
 
 
 struct util_cpu_caps {
    int nr_cpus;
 
    /* Feature flags */
    int x86_cpu_type;
    unsigned cacheline;
+   unsigned cores_per_L3;
 
    unsigned has_intel:1;
    unsigned has_tsc:1;
    unsigned has_mmx:1;
    unsigned has_mmx2:1;
    unsigned has_sse:1;
    unsigned has_sse2:1;
    unsigned has_sse3:1;
    unsigned has_ssse3:1;
    unsigned has_sse4_1:1;
-- 
2.17.1

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