From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/Makefile.sources | 1 +
src/gallium/drivers/radeonsi/meson.build | 1 +
src/gallium/drivers/radeonsi/si_pipe.h | 6 +
src/gallium/drivers/radeonsi/si_query.c | 219 +-----------
.../drivers/radeonsi/si_shaderlib_tgsi.c | 336 ++++++++++++++++++
src/gallium/drivers/radeonsi/si_state.h | 2 -
src/gallium/drivers/radeonsi/si_state_draw.c | 2 +-
.../drivers/radeonsi/si_state_shaders.c | 100 +-----
8 files changed, 348 insertions(+), 319 deletions(-)
create mode 100644 src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c
diff --git a/src/gallium/drivers/radeonsi/Makefile.sources
b/src/gallium/drivers/radeonsi/Makefile.sources
index c052e8dbeb3..b52db3a0598 100644
--- a/src/gallium/drivers/radeonsi/Makefile.sources
+++ b/src/gallium/drivers/radeonsi/Makefile.sources
@@ -28,20 +28,21 @@ C_SOURCES := \
si_public.h \
si_query.c \
si_query.h \
si_shader.c \
si_shader.h \
si_shader_internal.h \
si_shader_nir.c \
si_shader_tgsi_alu.c \
si_shader_tgsi_mem.c \
si_shader_tgsi_setup.c \
+ si_shaderlib_tgsi.c \
si_state.c \
si_state_binning.c \
si_state_draw.c \
si_state_msaa.c \
si_state_shaders.c \
si_state_streamout.c \
si_state_viewport.c \
si_state.h \
si_test_clearbuffer.c \
si_test_dma.c \
diff --git a/src/gallium/drivers/radeonsi/meson.build
b/src/gallium/drivers/radeonsi/meson.build
index 9e249adc61e..c24b55470a2 100644
--- a/src/gallium/drivers/radeonsi/meson.build
+++ b/src/gallium/drivers/radeonsi/meson.build
@@ -44,20 +44,21 @@ files_libradeonsi = files(
'si_public.h',
'si_query.c',
'si_query.h',
'si_shader.c',
'si_shader.h',
'si_shader_internal.h',
'si_shader_nir.c',
'si_shader_tgsi_alu.c',
'si_shader_tgsi_mem.c',
'si_shader_tgsi_setup.c',
+ 'si_shaderlib_tgsi.c',
'si_state.c',
'si_state.h',
'si_state_binning.c',
'si_state_draw.c',
'si_state_msaa.c',
'si_state_shaders.c',
'si_state_streamout.c',
'si_state_viewport.c',
'si_test_clearbuffer.c',
'si_test_dma.c',
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 2f77cc741bf..6bf9f2ed6d3 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1195,20 +1195,26 @@ void si_init_perfcounters(struct si_screen *screen);
/* si_pipe.c */
bool si_check_device_reset(struct si_context *sctx);
/* si_query.c */
void si_init_screen_query_functions(struct si_screen *sscreen);
void si_init_query_functions(struct si_context *sctx);
void si_suspend_queries(struct si_context *sctx);
void si_resume_queries(struct si_context *sctx);
+/* si_shaderlib_tgsi.c */
+void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
+ unsigned num_layers);
+void *si_create_fixed_func_tcs(struct si_context *sctx);
+void *si_create_query_result_cs(struct si_context *sctx);
+
/* si_test_dma.c */
void si_test_dma(struct si_screen *sscreen);
/* si_test_clearbuffer.c */
void si_test_clearbuffer_perf(struct si_screen *sscreen);
/* si_uvd.c */
struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
const struct pipe_video_codec
*templ);
diff --git a/src/gallium/drivers/radeonsi/si_query.c
b/src/gallium/drivers/radeonsi/si_query.c
index e29ce7150bd..f768b531139 100644
--- a/src/gallium/drivers/radeonsi/si_query.c
+++ b/src/gallium/drivers/radeonsi/si_query.c
@@ -23,21 +23,20 @@
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "si_pipe.h"
#include "si_query.h"
#include "util/u_memory.h"
#include "util/u_upload_mgr.h"
#include "util/os_time.h"
#include "util/u_suballoc.h"
-#include "tgsi/tgsi_text.h"
#include "amd/common/sid.h"
#define SI_MAX_STREAMS 4
struct si_hw_query_params {
unsigned start_offset;
unsigned end_offset;
unsigned fence_offset;
unsigned pair_stride;
unsigned pair_count;
@@ -1382,236 +1381,20 @@ bool si_query_hw_get_result(struct si_context *sctx,
}
/* Convert the time to expected units. */
if (rquery->type == PIPE_QUERY_TIME_ELAPSED ||
rquery->type == PIPE_QUERY_TIMESTAMP) {
result->u64 = (1000000 * result->u64) /
sscreen->info.clock_crystal_freq;
}
return true;
}
-/* Create the compute shader that is used to collect the results.
- *
- * One compute grid with a single thread is launched for every query result
- * buffer. The thread (optionally) reads a previous summary buffer, then
- * accumulates data from the query result buffer, and writes the result either
- * to a summary buffer to be consumed by the next grid invocation or to the
- * user-supplied buffer.
- *
- * Data layout:
- *
- * CONST
- * 0.x = end_offset
- * 0.y = result_stride
- * 0.z = result_count
- * 0.w = bit field:
- * 1: read previously accumulated values
- * 2: write accumulated values for chaining
- * 4: write result available
- * 8: convert result to boolean (0/1)
- * 16: only read one dword and use that as result
- * 32: apply timestamp conversion
- * 64: store full 64 bits result
- * 128: store signed 32 bits result
- * 256: SO_OVERFLOW mode: take the difference of two successive
half-pairs
- * 1.x = fence_offset
- * 1.y = pair_stride
- * 1.z = pair_count
- *
- * BUFFER[0] = query result buffer
- * BUFFER[1] = previous summary buffer
- * BUFFER[2] = next summary buffer or user-supplied buffer
- */
-static void si_create_query_result_shader(struct si_context *sctx)
-{
- /* TEMP[0].xy = accumulated result so far
- * TEMP[0].z = result not available
- *
- * TEMP[1].x = current result index
- * TEMP[1].y = current pair index
- */
- static const char text_tmpl[] =
- "COMP\n"
- "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
- "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
- "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
- "DCL BUFFER[0]\n"
- "DCL BUFFER[1]\n"
- "DCL BUFFER[2]\n"
- "DCL CONST[0][0..1]\n"
- "DCL TEMP[0..5]\n"
- "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
- "IMM[1] UINT32 {1, 2, 4, 8}\n"
- "IMM[2] UINT32 {16, 32, 64, 128}\n"
- "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp
conversion */
- "IMM[4] UINT32 {256, 0, 0, 0}\n"
-
- "AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n"
- "UIF TEMP[5]\n"
- /* Check result availability. */
- "LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n"
- "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
- "MOV TEMP[1], TEMP[0].zzzz\n"
- "NOT TEMP[0].z, TEMP[0].zzzz\n"
-
- /* Load result if available. */
- "UIF TEMP[1]\n"
- "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
- "ENDIF\n"
- "ELSE\n"
- /* Load previously accumulated result if requested. */
- "MOV TEMP[0], IMM[0].xxxx\n"
- "AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n"
- "UIF TEMP[4]\n"
- "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
- "ENDIF\n"
-
- "MOV TEMP[1].x, IMM[0].xxxx\n"
- "BGNLOOP\n"
- /* Break if accumulated result so far is not
available. */
- "UIF TEMP[0].zzzz\n"
- "BRK\n"
- "ENDIF\n"
-
- /* Break if result_index >= result_count. */
- "USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n"
- "UIF TEMP[5]\n"
- "BRK\n"
- "ENDIF\n"
-
- /* Load fence and check result availability */
- "UMAD TEMP[5].x, TEMP[1].xxxx,
CONST[0][0].yyyy, CONST[0][1].xxxx\n"
- "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
- "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
- "NOT TEMP[0].z, TEMP[0].zzzz\n"
- "UIF TEMP[0].zzzz\n"
- "BRK\n"
- "ENDIF\n"
-
- "MOV TEMP[1].y, IMM[0].xxxx\n"
- "BGNLOOP\n"
- /* Load start and end. */
- "UMUL TEMP[5].x, TEMP[1].xxxx,
CONST[0][0].yyyy\n"
- "UMAD TEMP[5].x, TEMP[1].yyyy,
CONST[0][1].yyyy, TEMP[5].xxxx\n"
- "LOAD TEMP[2].xy, BUFFER[0],
TEMP[5].xxxx\n"
-
- "UADD TEMP[5].y, TEMP[5].xxxx,
CONST[0][0].xxxx\n"
- "LOAD TEMP[3].xy, BUFFER[0],
TEMP[5].yyyy\n"
-
- "U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n"
-
- "AND TEMP[5].z, CONST[0][0].wwww,
IMM[4].xxxx\n"
- "UIF TEMP[5].zzzz\n"
- /* Load second start/end
half-pair and
- * take the difference
- */
- "UADD TEMP[5].xy, TEMP[5],
IMM[1].wwww\n"
- "LOAD TEMP[2].xy, BUFFER[0],
TEMP[5].xxxx\n"
- "LOAD TEMP[3].xy, BUFFER[0],
TEMP[5].yyyy\n"
-
- "U64ADD TEMP[3].xy, TEMP[3],
-TEMP[2]\n"
- "U64ADD TEMP[4].xy, TEMP[4],
-TEMP[3]\n"
- "ENDIF\n"
-
- "U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n"
-
- /* Increment pair index */
- "UADD TEMP[1].y, TEMP[1].yyyy,
IMM[1].xxxx\n"
- "USGE TEMP[5], TEMP[1].yyyy,
CONST[0][1].zzzz\n"
- "UIF TEMP[5]\n"
- "BRK\n"
- "ENDIF\n"
- "ENDLOOP\n"
-
- /* Increment result index */
- "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
- "ENDLOOP\n"
- "ENDIF\n"
-
- "AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n"
- "UIF TEMP[4]\n"
- /* Store accumulated data for chaining. */
- "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
- "ELSE\n"
- "AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n"
- "UIF TEMP[4]\n"
- /* Store result availability. */
- "NOT TEMP[0].z, TEMP[0]\n"
- "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
- "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
-
- "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
- "UIF TEMP[4]\n"
- "STORE BUFFER[2].y, IMM[0].xxxx,
IMM[0].xxxx\n"
- "ENDIF\n"
- "ELSE\n"
- /* Store result if it is available. */
- "NOT TEMP[4], TEMP[0].zzzz\n"
- "UIF TEMP[4]\n"
- /* Apply timestamp conversion */
- "AND TEMP[4], CONST[0][0].wwww,
IMM[2].yyyy\n"
- "UIF TEMP[4]\n"
- "U64MUL TEMP[0].xy, TEMP[0],
IMM[3].xyxy\n"
- "U64DIV TEMP[0].xy, TEMP[0],
IMM[3].zwzw\n"
- "ENDIF\n"
-
- /* Convert to boolean */
- "AND TEMP[4], CONST[0][0].wwww,
IMM[1].wwww\n"
- "UIF TEMP[4]\n"
- "U64SNE TEMP[0].x,
TEMP[0].xyxy, IMM[4].zwzw\n"
- "AND TEMP[0].x, TEMP[0].xxxx,
IMM[1].xxxx\n"
- "MOV TEMP[0].y, IMM[0].xxxx\n"
- "ENDIF\n"
-
- "AND TEMP[4], CONST[0][0].wwww,
IMM[2].zzzz\n"
- "UIF TEMP[4]\n"
- "STORE BUFFER[2].xy,
IMM[0].xxxx, TEMP[0].xyxy\n"
- "ELSE\n"
- /* Clamping */
- "UIF TEMP[0].yyyy\n"
- "MOV TEMP[0].x,
IMM[0].wwww\n"
- "ENDIF\n"
-
- "AND TEMP[4], CONST[0][0].wwww,
IMM[2].wwww\n"
- "UIF TEMP[4]\n"
- "UMIN TEMP[0].x,
TEMP[0].xxxx, IMM[0].zzzz\n"
- "ENDIF\n"
-
- "STORE BUFFER[2].x,
IMM[0].xxxx, TEMP[0].xxxx\n"
- "ENDIF\n"
- "ENDIF\n"
- "ENDIF\n"
- "ENDIF\n"
-
- "END\n";
-
- char text[sizeof(text_tmpl) + 32];
- struct tgsi_token tokens[1024];
- struct pipe_compute_state state = {};
-
- /* Hard code the frequency into the shader so that the backend can
- * use the full range of optimizations for divide-by-constant.
- */
- snprintf(text, sizeof(text), text_tmpl,
- sctx->screen->info.clock_crystal_freq);
-
- if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
- assert(false);
- return;
- }
-
- state.ir_type = PIPE_SHADER_IR_TGSI;
- state.prog = tokens;
-
- sctx->query_result_shader = sctx->b.create_compute_state(&sctx->b,
&state);
-}
-
static void si_restore_qbo_state(struct si_context *sctx,
struct si_qbo_state *st)
{
sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0,
&st->saved_const0);
pipe_resource_reference(&st->saved_const0.buffer, NULL);
sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3,
st->saved_ssbo);
for (unsigned i = 0; i < 3; ++i)
@@ -1640,21 +1423,21 @@ static void si_query_hw_get_result_resource(struct
si_context *sctx,
uint32_t end_offset;
uint32_t result_stride;
uint32_t result_count;
uint32_t config;
uint32_t fence_offset;
uint32_t pair_stride;
uint32_t pair_count;
} consts;
if (!sctx->query_result_shader) {
- si_create_query_result_shader(sctx);
+ sctx->query_result_shader = si_create_query_result_cs(sctx);
if (!sctx->query_result_shader)
return;
}
if (query->buffer.previous) {
u_suballocator_alloc(sctx->allocator_zeroed_memory, 16, 16,
&tmp_buffer_offset, &tmp_buffer);
if (!tmp_buffer)
return;
}
diff --git a/src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c
b/src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c
new file mode 100644
index 00000000000..45bc93ed782
--- /dev/null
+++ b/src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c
@@ -0,0 +1,336 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "si_pipe.h"
+#include "tgsi/tgsi_text.h"
+#include "tgsi/tgsi_ureg.h"
+
+void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
+ unsigned num_layers)
+{
+ unsigned vs_blit_property;
+ void **vs;
+
+ switch (type) {
+ case UTIL_BLITTER_ATTRIB_NONE:
+ vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
+ &sctx->vs_blit_pos;
+ vs_blit_property = SI_VS_BLIT_SGPRS_POS;
+ break;
+ case UTIL_BLITTER_ATTRIB_COLOR:
+ vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
+ &sctx->vs_blit_color;
+ vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
+ break;
+ case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
+ case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
+ assert(num_layers == 1);
+ vs = &sctx->vs_blit_texcoord;
+ vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
+ break;
+ default:
+ assert(0);
+ return NULL;
+ }
+ if (*vs)
+ return *vs;
+
+ struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
+ if (!ureg)
+ return NULL;
+
+ /* Tell the shader to load VS inputs from SGPRs: */
+ ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
+ ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
+
+ /* This is just a pass-through shader with 1-3 MOV instructions. */
+ ureg_MOV(ureg,
+ ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
+ ureg_DECL_vs_input(ureg, 0));
+
+ if (type != UTIL_BLITTER_ATTRIB_NONE) {
+ ureg_MOV(ureg,
+ ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
+ ureg_DECL_vs_input(ureg, 1));
+ }
+
+ if (num_layers > 1) {
+ struct ureg_src instance_id =
+ ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID,
0);
+ struct ureg_dst layer =
+ ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
+
+ ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
+ ureg_scalar(instance_id, TGSI_SWIZZLE_X));
+ }
+ ureg_END(ureg);
+
+ *vs = ureg_create_shader_and_destroy(ureg, &sctx->b);
+ return *vs;
+}
+
+/**
+ * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
+ * VS passes its outputs to TES directly, so the fixed-function shader only
+ * has to write TESSOUTER and TESSINNER.
+ */
+void *si_create_fixed_func_tcs(struct si_context *sctx)
+{
+ struct ureg_src outer, inner;
+ struct ureg_dst tessouter, tessinner;
+ struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
+
+ if (!ureg)
+ return NULL;
+
+ outer = ureg_DECL_system_value(ureg,
+ TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
+ inner = ureg_DECL_system_value(ureg,
+ TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
+
+ tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
+ tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
+
+ ureg_MOV(ureg, tessouter, outer);
+ ureg_MOV(ureg, tessinner, inner);
+ ureg_END(ureg);
+
+ return ureg_create_shader_and_destroy(ureg, &sctx->b);
+}
+
+/* Create the compute shader that is used to collect the results.
+ *
+ * One compute grid with a single thread is launched for every query result
+ * buffer. The thread (optionally) reads a previous summary buffer, then
+ * accumulates data from the query result buffer, and writes the result either
+ * to a summary buffer to be consumed by the next grid invocation or to the
+ * user-supplied buffer.
+ *
+ * Data layout:
+ *
+ * CONST
+ * 0.x = end_offset
+ * 0.y = result_stride
+ * 0.z = result_count
+ * 0.w = bit field:
+ * 1: read previously accumulated values
+ * 2: write accumulated values for chaining
+ * 4: write result available
+ * 8: convert result to boolean (0/1)
+ * 16: only read one dword and use that as result
+ * 32: apply timestamp conversion
+ * 64: store full 64 bits result
+ * 128: store signed 32 bits result
+ * 256: SO_OVERFLOW mode: take the difference of two successive
half-pairs
+ * 1.x = fence_offset
+ * 1.y = pair_stride
+ * 1.z = pair_count
+ *
+ * BUFFER[0] = query result buffer
+ * BUFFER[1] = previous summary buffer
+ * BUFFER[2] = next summary buffer or user-supplied buffer
+ */
+void *si_create_query_result_cs(struct si_context *sctx)
+{
+ /* TEMP[0].xy = accumulated result so far
+ * TEMP[0].z = result not available
+ *
+ * TEMP[1].x = current result index
+ * TEMP[1].y = current pair index
+ */
+ static const char text_tmpl[] =
+ "COMP\n"
+ "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
+ "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
+ "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
+ "DCL BUFFER[0]\n"
+ "DCL BUFFER[1]\n"
+ "DCL BUFFER[2]\n"
+ "DCL CONST[0][0..1]\n"
+ "DCL TEMP[0..5]\n"
+ "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
+ "IMM[1] UINT32 {1, 2, 4, 8}\n"
+ "IMM[2] UINT32 {16, 32, 64, 128}\n"
+ "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp
conversion */
+ "IMM[4] UINT32 {256, 0, 0, 0}\n"
+
+ "AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n"
+ "UIF TEMP[5]\n"
+ /* Check result availability. */
+ "LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n"
+ "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
+ "MOV TEMP[1], TEMP[0].zzzz\n"
+ "NOT TEMP[0].z, TEMP[0].zzzz\n"
+
+ /* Load result if available. */
+ "UIF TEMP[1]\n"
+ "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
+ "ENDIF\n"
+ "ELSE\n"
+ /* Load previously accumulated result if requested. */
+ "MOV TEMP[0], IMM[0].xxxx\n"
+ "AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n"
+ "UIF TEMP[4]\n"
+ "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
+ "ENDIF\n"
+
+ "MOV TEMP[1].x, IMM[0].xxxx\n"
+ "BGNLOOP\n"
+ /* Break if accumulated result so far is not
available. */
+ "UIF TEMP[0].zzzz\n"
+ "BRK\n"
+ "ENDIF\n"
+
+ /* Break if result_index >= result_count. */
+ "USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n"
+ "UIF TEMP[5]\n"
+ "BRK\n"
+ "ENDIF\n"
+
+ /* Load fence and check result availability */
+ "UMAD TEMP[5].x, TEMP[1].xxxx,
CONST[0][0].yyyy, CONST[0][1].xxxx\n"
+ "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
+ "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
+ "NOT TEMP[0].z, TEMP[0].zzzz\n"
+ "UIF TEMP[0].zzzz\n"
+ "BRK\n"
+ "ENDIF\n"
+
+ "MOV TEMP[1].y, IMM[0].xxxx\n"
+ "BGNLOOP\n"
+ /* Load start and end. */
+ "UMUL TEMP[5].x, TEMP[1].xxxx,
CONST[0][0].yyyy\n"
+ "UMAD TEMP[5].x, TEMP[1].yyyy,
CONST[0][1].yyyy, TEMP[5].xxxx\n"
+ "LOAD TEMP[2].xy, BUFFER[0],
TEMP[5].xxxx\n"
+
+ "UADD TEMP[5].y, TEMP[5].xxxx,
CONST[0][0].xxxx\n"
+ "LOAD TEMP[3].xy, BUFFER[0],
TEMP[5].yyyy\n"
+
+ "U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n"
+
+ "AND TEMP[5].z, CONST[0][0].wwww,
IMM[4].xxxx\n"
+ "UIF TEMP[5].zzzz\n"
+ /* Load second start/end
half-pair and
+ * take the difference
+ */
+ "UADD TEMP[5].xy, TEMP[5],
IMM[1].wwww\n"
+ "LOAD TEMP[2].xy, BUFFER[0],
TEMP[5].xxxx\n"
+ "LOAD TEMP[3].xy, BUFFER[0],
TEMP[5].yyyy\n"
+
+ "U64ADD TEMP[3].xy, TEMP[3],
-TEMP[2]\n"
+ "U64ADD TEMP[4].xy, TEMP[4],
-TEMP[3]\n"
+ "ENDIF\n"
+
+ "U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n"
+
+ /* Increment pair index */
+ "UADD TEMP[1].y, TEMP[1].yyyy,
IMM[1].xxxx\n"
+ "USGE TEMP[5], TEMP[1].yyyy,
CONST[0][1].zzzz\n"
+ "UIF TEMP[5]\n"
+ "BRK\n"
+ "ENDIF\n"
+ "ENDLOOP\n"
+
+ /* Increment result index */
+ "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
+ "ENDLOOP\n"
+ "ENDIF\n"
+
+ "AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n"
+ "UIF TEMP[4]\n"
+ /* Store accumulated data for chaining. */
+ "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
+ "ELSE\n"
+ "AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n"
+ "UIF TEMP[4]\n"
+ /* Store result availability. */
+ "NOT TEMP[0].z, TEMP[0]\n"
+ "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
+ "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
+
+ "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
+ "UIF TEMP[4]\n"
+ "STORE BUFFER[2].y, IMM[0].xxxx,
IMM[0].xxxx\n"
+ "ENDIF\n"
+ "ELSE\n"
+ /* Store result if it is available. */
+ "NOT TEMP[4], TEMP[0].zzzz\n"
+ "UIF TEMP[4]\n"
+ /* Apply timestamp conversion */
+ "AND TEMP[4], CONST[0][0].wwww,
IMM[2].yyyy\n"
+ "UIF TEMP[4]\n"
+ "U64MUL TEMP[0].xy, TEMP[0],
IMM[3].xyxy\n"
+ "U64DIV TEMP[0].xy, TEMP[0],
IMM[3].zwzw\n"
+ "ENDIF\n"
+
+ /* Convert to boolean */
+ "AND TEMP[4], CONST[0][0].wwww,
IMM[1].wwww\n"
+ "UIF TEMP[4]\n"
+ "U64SNE TEMP[0].x,
TEMP[0].xyxy, IMM[4].zwzw\n"
+ "AND TEMP[0].x, TEMP[0].xxxx,
IMM[1].xxxx\n"
+ "MOV TEMP[0].y, IMM[0].xxxx\n"
+ "ENDIF\n"
+
+ "AND TEMP[4], CONST[0][0].wwww,
IMM[2].zzzz\n"
+ "UIF TEMP[4]\n"
+ "STORE BUFFER[2].xy,
IMM[0].xxxx, TEMP[0].xyxy\n"
+ "ELSE\n"
+ /* Clamping */
+ "UIF TEMP[0].yyyy\n"
+ "MOV TEMP[0].x,
IMM[0].wwww\n"
+ "ENDIF\n"
+
+ "AND TEMP[4], CONST[0][0].wwww,
IMM[2].wwww\n"
+ "UIF TEMP[4]\n"
+ "UMIN TEMP[0].x,
TEMP[0].xxxx, IMM[0].zzzz\n"
+ "ENDIF\n"
+
+ "STORE BUFFER[2].x,
IMM[0].xxxx, TEMP[0].xxxx\n"
+ "ENDIF\n"
+ "ENDIF\n"
+ "ENDIF\n"
+ "ENDIF\n"
+
+ "END\n";
+
+ char text[sizeof(text_tmpl) + 32];
+ struct tgsi_token tokens[1024];
+ struct pipe_compute_state state = {};
+
+ /* Hard code the frequency into the shader so that the backend can
+ * use the full range of optimizations for divide-by-constant.
+ */
+ snprintf(text, sizeof(text), text_tmpl,
+ sctx->screen->info.clock_crystal_freq);
+
+ if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
+ assert(false);
+ return NULL;
+ }
+
+ state.ir_type = PIPE_SHADER_IR_TGSI;
+ state.prog = tokens;
+
+ return sctx->b.create_compute_state(&sctx->b, &state);
+}
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index 1edf5d646b6..3bf0e8e4daa 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -504,22 +504,20 @@ bool si_update_shaders(struct si_context *sctx);
void si_init_shader_functions(struct si_context *sctx);
bool si_init_shader_cache(struct si_screen *sscreen);
void si_destroy_shader_cache(struct si_screen *sscreen);
void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
struct util_queue_fence *ready_fence,
struct si_compiler_ctx_state
*compiler_ctx_state,
void *job, util_queue_execute_func execute);
void si_get_active_slot_masks(const struct tgsi_shader_info *info,
uint32_t *const_and_shader_buffers,
uint64_t *samplers_and_images);
-void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
- unsigned num_layers);
/* si_state_draw.c */
void si_init_ia_multi_vgt_param_table(struct si_context *sctx);
void si_emit_cache_flush(struct si_context *sctx);
void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
void si_draw_rectangle(struct blitter_context *blitter,
void *vertex_elements_cso,
blitter_get_vs_func get_vs,
int x1, int y1, int x2, int y2,
float depth, unsigned num_instances,
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index d901401f0bb..b1d7437edb9 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1536,21 +1536,21 @@ void si_draw_rectangle(struct blitter_context *blitter,
sizeof(float)*4);
break;
case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
sizeof(attrib->texcoord));
break;
case UTIL_BLITTER_ATTRIB_NONE:;
}
- pipe->bind_vs_state(pipe, si_get_blit_vs(sctx, type, num_instances));
+ pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
struct pipe_draw_info info = {};
info.mode = SI_PRIM_RECTANGLE_LIST;
info.count = 3;
info.instance_count = num_instances;
/* Don't set per-stage shader pointers for VS. */
sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
sctx->vertex_buffer_pointer_dirty = false;
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index de33d250301..0766d8cb7d8 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -20,21 +20,20 @@
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "si_build_pm4.h"
#include "gfx9d.h"
#include "compiler/nir/nir_serialize.h"
#include "tgsi/tgsi_parse.h"
-#include "tgsi/tgsi_ureg.h"
#include "util/hash_table.h"
#include "util/crc32.h"
#include "util/u_async_debug.h"
#include "util/u_memory.h"
#include "util/u_prim.h"
#include "util/disk_cache.h"
#include "util/mesa-sha1.h"
#include "ac_exp_param.h"
#include "ac_shader_util.h"
@@ -3093,52 +3092,20 @@ static void si_init_tess_factor_ring(struct si_context
*sctx)
}
/* Flush the context to re-emit the init_config state.
* This is done only once in a lifetime of a context.
*/
si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
sctx->initial_gfx_cs_size = 0; /* force flush */
si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
}
-/**
- * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
- * VS passes its outputs to TES directly, so the fixed-function shader only
- * has to write TESSOUTER and TESSINNER.
- */
-static void si_generate_fixed_func_tcs(struct si_context *sctx)
-{
- struct ureg_src outer, inner;
- struct ureg_dst tessouter, tessinner;
- struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
-
- if (!ureg)
- return; /* if we get here, we're screwed */
-
- assert(!sctx->fixed_func_tcs_shader.cso);
-
- outer = ureg_DECL_system_value(ureg,
- TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
- inner = ureg_DECL_system_value(ureg,
- TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
-
- tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
- tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
-
- ureg_MOV(ureg, tessouter, outer);
- ureg_MOV(ureg, tessinner, inner);
- ureg_END(ureg);
-
- sctx->fixed_func_tcs_shader.cso =
- ureg_create_shader_and_destroy(ureg, &sctx->b);
-}
-
static void si_update_vgt_shader_config(struct si_context *sctx)
{
/* Calculate the index of the config.
* 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
if (!*pm4) {
uint32_t stages = 0;
@@ -3202,21 +3169,22 @@ bool si_update_shaders(struct si_context *sctx)
}
if (sctx->tcs_shader.cso) {
r = si_shader_select(ctx, &sctx->tcs_shader,
&compiler_state);
if (r)
return false;
si_pm4_bind_state(sctx, hs,
sctx->tcs_shader.current->pm4);
} else {
if (!sctx->fixed_func_tcs_shader.cso) {
- si_generate_fixed_func_tcs(sctx);
+ sctx->fixed_func_tcs_shader.cso =
+ si_create_fixed_func_tcs(sctx);
if (!sctx->fixed_func_tcs_shader.cso)
return false;
}
r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
&compiler_state);
if (r)
return false;
si_pm4_bind_state(sctx, hs,
sctx->fixed_func_tcs_shader.current->pm4);
@@ -3381,84 +3349,20 @@ static void si_emit_scratch_state(struct si_context
*sctx)
radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
sctx->spi_tmpring_size);
if (sctx->scratch_buffer) {
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
sctx->scratch_buffer,
RADEON_USAGE_READWRITE,
RADEON_PRIO_SCRATCH_BUFFER);
}
}
-void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
- unsigned num_layers)
-{
- unsigned vs_blit_property;
- void **vs;
-
- switch (type) {
- case UTIL_BLITTER_ATTRIB_NONE:
- vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
- &sctx->vs_blit_pos;
- vs_blit_property = SI_VS_BLIT_SGPRS_POS;
- break;
- case UTIL_BLITTER_ATTRIB_COLOR:
- vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
- &sctx->vs_blit_color;
- vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
- break;
- case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
- case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
- assert(num_layers == 1);
- vs = &sctx->vs_blit_texcoord;
- vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
- break;
- default:
- assert(0);
- return NULL;
- }
- if (*vs)
- return *vs;
-
- struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
- if (!ureg)
- return NULL;
-
- /* Tell the shader to load VS inputs from SGPRs: */
- ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
- ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
-
- /* This is just a pass-through shader with 1-3 MOV instructions. */
- ureg_MOV(ureg,
- ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
- ureg_DECL_vs_input(ureg, 0));
-
- if (type != UTIL_BLITTER_ATTRIB_NONE) {
- ureg_MOV(ureg,
- ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
- ureg_DECL_vs_input(ureg, 1));
- }
-
- if (num_layers > 1) {
- struct ureg_src instance_id =
- ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID,
0);
- struct ureg_dst layer =
- ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
-
- ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
- ureg_scalar(instance_id, TGSI_SWIZZLE_X));
- }
- ureg_END(ureg);
-
- *vs = ureg_create_shader_and_destroy(ureg, &sctx->b);
- return *vs;
-}
-
void si_init_shader_functions(struct si_context *sctx)
{
sctx->atoms.s.spi_map.emit = si_emit_spi_map;
sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
sctx->b.create_vs_state = si_create_shader_selector;
sctx->b.create_tcs_state = si_create_shader_selector;
sctx->b.create_tes_state = si_create_shader_selector;
sctx->b.create_gs_state = si_create_shader_selector;
sctx->b.create_fs_state = si_create_shader_selector;
--
2.17.1
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