No functional change. Cc: <mesa-sta...@lists.freedesktop.org> Signed-off-by: Fredrik Höglund <fred...@kde.org> --- src/amd/vulkan/radv_meta_blit.c | 66 +++++++++++++++++++++++++-- src/amd/vulkan/radv_meta_blit2d.c | 66 +++++++++++++++++++++++++-- src/amd/vulkan/radv_meta_clear.c | 45 +++++++++++++++++- src/amd/vulkan/radv_meta_decompress.c | 22 ++++++++- src/amd/vulkan/radv_meta_fast_clear.c | 22 ++++++++- src/amd/vulkan/radv_meta_resolve.c | 22 ++++++++- src/amd/vulkan/radv_meta_resolve_fs.c | 22 ++++++++- 7 files changed, 253 insertions(+), 12 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c
index a6ee0cb7e93..c8aad8b38c8 100644
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -762,7 +762,27 @@ radv_device_init_meta_blit_color(struct radv_device
*device,
.preserveAttachmentCount = 1,
.pPreserveAttachments = (uint32_t[]) { 0 },
},
- .dependencyCount = 0,
+ .dependencyCount = 2,
+ .pDependencies =
(VkSubpassDependency[]) {
+ {
+
.srcSubpass = VK_SUBPASS_EXTERNAL,
+
.dstSubpass = 0,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ },
+ {
+
.srcSubpass = 0,
+
.dstSubpass = VK_SUBPASS_EXTERNAL,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ }
+ },
}, &device->meta_state.alloc,
&device->meta_state.blit.render_pass[key][j]);
if (result != VK_SUCCESS)
goto fail;
@@ -921,7 +941,27 @@ radv_device_init_meta_blit_depth(struct radv_device
*device,
.preserveAttachmentCount = 1,
.pPreserveAttachments = (uint32_t[]) { 0 },
},
- .dependencyCount = 0,
+ .dependencyCount = 2,
+ .pDependencies =
(VkSubpassDependency[]) {
+ {
+
.srcSubpass = VK_SUBPASS_EXTERNAL,
+
.dstSubpass = 0,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ },
+ {
+
.srcSubpass = 0,
+
.dstSubpass = VK_SUBPASS_EXTERNAL,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ }
+ },
}, &device->meta_state.alloc,
&device->meta_state.blit.depth_only_rp[ds_layout]);
if (result != VK_SUCCESS)
goto fail;
@@ -1082,7 +1122,27 @@ radv_device_init_meta_blit_stencil(struct radv_device
*device,
.preserveAttachmentCount = 1,
.pPreserveAttachments = (uint32_t[]) { 0 },
},
- .dependencyCount = 0,
+ .dependencyCount = 2,
+ .pDependencies =
(VkSubpassDependency[]) {
+ {
+
.srcSubpass = VK_SUBPASS_EXTERNAL,
+
.dstSubpass = 0,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ },
+ {
+
.srcSubpass = 0,
+
.dstSubpass = VK_SUBPASS_EXTERNAL,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ }
+ },
}, &device->meta_state.alloc,
&device->meta_state.blit.stencil_only_rp[ds_layout]);
}
if (result != VK_SUCCESS)
diff --git a/src/amd/vulkan/radv_meta_blit2d.c
b/src/amd/vulkan/radv_meta_blit2d.c
index 85e2d4678e9..eed5c62b4de 100644
--- a/src/amd/vulkan/radv_meta_blit2d.c
+++ b/src/amd/vulkan/radv_meta_blit2d.c
@@ -818,7 +818,27 @@ blit2d_init_color_pipeline(struct radv_device *device,
.preserveAttachmentCount = 1,
.pPreserveAttachments =
(uint32_t[]) { 0 },
},
- .dependencyCount = 0,
+ .dependencyCount = 2,
+ .pDependencies =
(VkSubpassDependency[]) {
+ {
+ .srcSubpass =
VK_SUBPASS_EXTERNAL,
+ .dstSubpass = 0,
+ .srcStageMask =
VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+ .dstStageMask =
VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+ .srcAccessMask = 0,
+ .dstAccessMask = 0,
+ .dependencyFlags = 0
+ },
+ {
+ .srcSubpass = 0,
+ .dstSubpass =
VK_SUBPASS_EXTERNAL,
+ .srcStageMask =
VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+ .dstStageMask =
VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+ .srcAccessMask = 0,
+ .dstAccessMask = 0,
+ .dependencyFlags = 0
+ }
+ }
}, &device->meta_state.alloc,
&device->meta_state.blit2d_render_passes[fs_key][dst_layout]);
}
}
@@ -981,7 +1001,27 @@ blit2d_init_depth_only_pipeline(struct radv_device
*device,
.preserveAttachmentCount = 1,
.pPreserveAttachments = (uint32_t[]) { 0 },
},
- .dependencyCount
= 0,
+ .dependencyCount
= 2,
+ .pDependencies =
(VkSubpassDependency[]) {
+ {
+
.srcSubpass = VK_SUBPASS_EXTERNAL,
+
.dstSubpass = 0,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ },
+ {
+
.srcSubpass = 0,
+
.dstSubpass = VK_SUBPASS_EXTERNAL,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ }
+ }
},
&device->meta_state.alloc, &device->meta_state.blit2d_depth_only_rp[ds_layout]);
}
}
@@ -1144,7 +1184,27 @@ blit2d_init_stencil_only_pipeline(struct radv_device
*device,
.preserveAttachmentCount = 1,
.pPreserveAttachments = (uint32_t[]) { 0 },
},
- .dependencyCount
= 0,
+ .dependencyCount
= 2,
+ .pDependencies =
(VkSubpassDependency[]) {
+ {
+
.srcSubpass = VK_SUBPASS_EXTERNAL,
+
.dstSubpass = 0,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ },
+ {
+
.srcSubpass = 0,
+
.dstSubpass = VK_SUBPASS_EXTERNAL,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ }
+ }
},
&device->meta_state.alloc,
&device->meta_state.blit2d_stencil_only_rp[ds_layout]);
}
}
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 2c0bb373873..6d1bcd2650a 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -229,7 +229,27 @@ create_color_renderpass(struct radv_device *device,
.preserveAttachmentCount
= 1,
.pPreserveAttachments =
(uint32_t[]) { 0 },
},
-
.dependencyCount = 0,
+
.dependencyCount = 2,
+ .pDependencies
= (VkSubpassDependency[]) {
+ {
+
.srcSubpass = VK_SUBPASS_EXTERNAL,
+
.dstSubpass = 0,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ },
+ {
+
.srcSubpass = 0,
+
.dstSubpass = VK_SUBPASS_EXTERNAL,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ }
+ },
},
&device->meta_state.alloc, pass);
}
@@ -475,7 +495,28 @@ create_depthstencil_renderpass(struct radv_device *device,
.preserveAttachmentCount
= 1,
.pPreserveAttachments =
(uint32_t[]) { 0 },
},
-
.dependencyCount = 0,
+
.dependencyCount = 2,
+ .pDependencies
= (VkSubpassDependency[]) {
+ {
+
.srcSubpass = VK_SUBPASS_EXTERNAL,
+
.dstSubpass = 0,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ },
+ {
+
.srcSubpass = 0,
+
.dstSubpass = VK_SUBPASS_EXTERNAL,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ }
+ },
+
},
&device->meta_state.alloc, render_pass);
}
diff --git a/src/amd/vulkan/radv_meta_decompress.c
b/src/amd/vulkan/radv_meta_decompress.c
index 1a8058c7cc5..87432ded4e9 100644
--- a/src/amd/vulkan/radv_meta_decompress.c
+++ b/src/amd/vulkan/radv_meta_decompress.c
@@ -67,7 +67,27 @@ create_pass(struct radv_device *device,
.preserveAttachmentCount
= 0,
.pPreserveAttachments =
NULL,
},
-
.dependencyCount = 0,
+
.dependencyCount = 2,
+ .pDependencies
= (VkSubpassDependency[]) {
+ {
+
.srcSubpass = VK_SUBPASS_EXTERNAL,
+
.dstSubpass = 0,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ },
+ {
+
.srcSubpass = 0,
+
.dstSubpass = VK_SUBPASS_EXTERNAL,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ }
+ }
},
alloc,
pass);
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c
b/src/amd/vulkan/radv_meta_fast_clear.c
index 041c9e44c45..c309b7f2bfa 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -221,7 +221,27 @@ create_pass(struct radv_device *device)
.preserveAttachmentCount
= 0,
.pPreserveAttachments =
NULL,
},
-
.dependencyCount = 0,
+
.dependencyCount = 2,
+ .pDependencies
= (VkSubpassDependency[]) {
+ {
+
.srcSubpass = VK_SUBPASS_EXTERNAL,
+
.dstSubpass = 0,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ },
+ {
+
.srcSubpass = 0,
+
.dstSubpass = VK_SUBPASS_EXTERNAL,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ }
+ }
},
alloc,
&device->meta_state.fast_clear_flush.pass);
diff --git a/src/amd/vulkan/radv_meta_resolve.c
b/src/amd/vulkan/radv_meta_resolve.c
index d4d3552f317..5ae8d34e95d 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -97,7 +97,27 @@ create_pass(struct radv_device *device, VkFormat vk_format,
VkRenderPass *pass)
.preserveAttachmentCount
= 0,
.pPreserveAttachments =
NULL,
},
-
.dependencyCount = 0,
+
.dependencyCount = 2,
+ .pDependencies
= (VkSubpassDependency[]) {
+ {
+
.srcSubpass = VK_SUBPASS_EXTERNAL,
+
.dstSubpass = 0,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ },
+ {
+
.srcSubpass = 0,
+
.dstSubpass = VK_SUBPASS_EXTERNAL,
+
.srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+
.dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+
.srcAccessMask = 0,
+
.dstAccessMask = 0,
+
.dependencyFlags = 0
+ }
+ }
},
alloc,
pass);
diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c
b/src/amd/vulkan/radv_meta_resolve_fs.c
index ef8c1d8b1da..e4c82d29cb8 100644
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -245,7 +245,27 @@ create_resolve_pipeline(struct radv_device *device,
.preserveAttachmentCount = 1,
.pPreserveAttachments =
(uint32_t[]) { 0 },
},
- .dependencyCount = 0,
+ .dependencyCount = 2,
+ .pDependencies =
(VkSubpassDependency[]) {
+ {
+ .srcSubpass =
VK_SUBPASS_EXTERNAL,
+ .dstSubpass = 0,
+ .srcStageMask =
VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+ .dstStageMask =
VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+ .srcAccessMask = 0,
+ .dstAccessMask = 0,
+ .dependencyFlags = 0
+ },
+ {
+ .srcSubpass = 0,
+ .dstSubpass =
VK_SUBPASS_EXTERNAL,
+ .srcStageMask =
VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
+ .dstStageMask =
VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
+ .srcAccessMask = 0,
+ .dstAccessMask = 0,
+ .dependencyFlags = 0
+ }
+ },
}, &device->meta_state.alloc, rp + dst_layout);
}
--
2.17.0
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