From: Marek Olšák <marek.ol...@amd.com> --- .../drivers/radeonsi/si_state_binning.c | 20 +------------------ 1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c
b/src/gallium/drivers/radeonsi/si_state_binning.c
index c49f7c7177f..5c794376753 100644
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -47,21 +47,21 @@ static struct uvec2 si_find_bin_size(struct si_screen
*sscreen,
unsigned log_num_rb_per_se =
util_logbase2_ceil(sscreen->info.num_render_backends /
sscreen->info.max_se);
unsigned log_num_se = util_logbase2_ceil(sscreen->info.max_se);
unsigned i;
/* Get the chip-specific subtable. */
const struct si_bin_size_map *subtable =
&table[log_num_rb_per_se][log_num_se][0];
- for (i = 0; subtable[i].start != UINT_MAX; i++) {
+ for (i = 0; subtable[i].bin_size_x != 0; i++) {
if (sum >= subtable[i].start && sum < subtable[i + 1].start)
break;
}
struct uvec2 size = {subtable[i].bin_size_x, subtable[i].bin_size_y};
return size;
}
static struct uvec2 si_get_color_bin_size(struct si_context *sctx,
unsigned cb_target_enabled_4bit)
@@ -90,104 +90,95 @@ static struct uvec2 si_get_color_bin_size(struct
si_context *sctx,
static const si_bin_size_subtable table[] = {
{
/* One RB / SE */
{
/* One shader engine */
{ 0, 128, 128 },
{ 1, 64, 128 },
{ 2, 32, 128 },
{ 3, 16, 128 },
{ 17, 0, 0 },
- { UINT_MAX, 0, 0 },
},
{
/* Two shader engines */
{ 0, 128, 128 },
{ 2, 64, 128 },
{ 3, 32, 128 },
{ 5, 16, 128 },
{ 17, 0, 0 },
- { UINT_MAX, 0, 0 },
},
{
/* Four shader engines */
{ 0, 128, 128 },
{ 3, 64, 128 },
{ 5, 16, 128 },
{ 17, 0, 0 },
- { UINT_MAX, 0, 0 },
},
},
{
/* Two RB / SE */
{
/* One shader engine */
{ 0, 128, 128 },
{ 2, 64, 128 },
{ 3, 32, 128 },
{ 9, 16, 128 },
{ 33, 0, 0 },
- { UINT_MAX, 0, 0 },
},
{
/* Two shader engines */
{ 0, 128, 128 },
{ 3, 64, 128 },
{ 5, 32, 128 },
{ 9, 16, 128 },
{ 33, 0, 0 },
- { UINT_MAX, 0, 0 },
},
{
/* Four shader engines */
{ 0, 256, 256 },
{ 2, 128, 256 },
{ 3, 128, 128 },
{ 5, 64, 128 },
{ 9, 16, 128 },
{ 33, 0, 0 },
- { UINT_MAX, 0, 0 },
},
},
{
/* Four RB / SE */
{
/* One shader engine */
{ 0, 128, 256 },
{ 2, 128, 128 },
{ 3, 64, 128 },
{ 5, 32, 128 },
{ 9, 16, 128 },
{ 17, 0, 0 },
- { UINT_MAX, 0, 0 },
},
{
/* Two shader engines */
{ 0, 256, 256 },
{ 2, 128, 256 },
{ 3, 128, 128 },
{ 5, 64, 128 },
{ 9, 32, 128 },
{ 17, 16, 128 },
{ 33, 0, 0 },
- { UINT_MAX, 0, 0 },
},
{
/* Four shader engines */
{ 0, 256, 512 },
{ 2, 128, 512 },
{ 3, 64, 512 },
{ 5, 32, 512 },
{ 9, 32, 256 },
{ 17, 32, 128 },
{ 33, 0, 0 },
- { UINT_MAX, 0, 0 },
},
},
};
return si_find_bin_size(sctx->screen, table, sum);
}
static struct uvec2 si_get_depth_bin_size(struct si_context *sctx)
{
struct si_state_dsa *dsa = sctx->queued.named.dsa;
@@ -211,121 +202,112 @@ static struct uvec2 si_get_depth_bin_size(struct
si_context *sctx)
{
// One RB / SE
{
// One shader engine
{ 0, 64, 512 },
{ 2, 64, 256 },
{ 4, 64, 128 },
{ 7, 32, 128 },
{ 13, 16, 128 },
{ 49, 0, 0 },
- { UINT_MAX, 0, 0 },
},
{
// Two shader engines
{ 0, 128, 512 },
{ 2, 64, 512 },
{ 4, 64, 256 },
{ 7, 64, 128 },
{ 13, 32, 128 },
{ 25, 16, 128 },
{ 49, 0, 0 },
- { UINT_MAX, 0, 0 },
},
{
// Four shader engines
{ 0, 256, 512 },
{ 2, 128, 512 },
{ 4, 64, 512 },
{ 7, 64, 256 },
{ 13, 64, 128 },
{ 25, 16, 128 },
{ 49, 0, 0 },
- { UINT_MAX, 0, 0 },
},
},
{
// Two RB / SE
{
// One shader engine
{ 0, 128, 512 },
{ 2, 64, 512 },
{ 4, 64, 256 },
{ 7, 64, 128 },
{ 13, 32, 128 },
{ 25, 16, 128 },
{ 97, 0, 0 },
- { UINT_MAX, 0, 0 },
},
{
// Two shader engines
{ 0, 256, 512 },
{ 2, 128, 512 },
{ 4, 64, 512 },
{ 7, 64, 256 },
{ 13, 64, 128 },
{ 25, 32, 128 },
{ 49, 16, 128 },
{ 97, 0, 0 },
- { UINT_MAX, 0, 0 },
},
{
// Four shader engines
{ 0, 512, 512 },
{ 2, 256, 512 },
{ 4, 128, 512 },
{ 7, 64, 512 },
{ 13, 64, 256 },
{ 25, 64, 128 },
{ 49, 16, 128 },
{ 97, 0, 0 },
- { UINT_MAX, 0, 0 },
},
},
{
// Four RB / SE
{
// One shader engine
{ 0, 256, 512 },
{ 2, 128, 512 },
{ 4, 64, 512 },
{ 7, 64, 256 },
{ 13, 64, 128 },
{ 25, 32, 128 },
{ 49, 16, 128 },
{ 193, 0, 0 },
- { UINT_MAX, 0, 0 },
},
{
// Two shader engines
{ 0, 512, 512 },
{ 2, 256, 512 },
{ 4, 128, 512 },
{ 7, 64, 512 },
{ 13, 64, 256 },
{ 25, 64, 128 },
{ 49, 32, 128 },
{ 97, 16, 128 },
{ 193, 0, 0 },
- { UINT_MAX, 0, 0 },
},
{
// Four shader engines
{ 0, 512, 512 },
{ 4, 256, 512 },
{ 7, 128, 512 },
{ 13, 64, 512 },
{ 25, 32, 512 },
{ 49, 32, 256 },
{ 97, 16, 128 },
{ 193, 0, 0 },
- { UINT_MAX, 0, 0 },
},
},
};
return si_find_bin_size(sctx->screen, table, sum);
}
static void si_emit_dpbb_disable(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
--
2.17.0
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