Quoting Scott D Phillips (2018-04-03 21:05:44)
> Removes a place where gtt mapping is used.
>
> Reviewed-by: Nanley Chery <nanley.g.ch...@intel.com>
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 58ffe868d0d..d8a6fc692ab 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -3735,7 +3735,8 @@ intel_miptree_map(struct brw_context *brw,
> #if defined(USE_SSE41)
> } else if (!(mode & GL_MAP_WRITE_BIT) &&
> !mt->compressed && cpu_has_sse4_1 &&
> - (mt->surf.row_pitch % 16 == 0)) {
> + (mt->surf.row_pitch % 16 == 0) &&
> + (mt->surf.tiling == ISL_TILING_LINEAR)) {
> intel_miptree_map_movntdqa(brw, mt, map, level, slice);
> #endif
> } else if (mt->surf.tiling != ISL_TILING_LINEAR &&
> @@ -3781,6 +3782,7 @@ intel_miptree_unmap(struct brw_context *brw,
> } else if (!(map->mode & GL_MAP_WRITE_BIT) &&
> !mt->compressed && cpu_has_sse4_1 &&
> (mt->surf.row_pitch % 16 == 0) &&
> + (mt->surf.tiling == ISL_TILING_LINEAR) &&
> map->buffer) {
> intel_miptree_unmap_movntdqa(brw, mt, map, level, slice);
And the rules in brw_bo_map() do mean that it will try to use WB/WC
mmaps. And the new map from patch 3 provides the tiled accesss WC.
We could fix up the alignment requirement here to avoid falling through
to map_map.
Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>
-Chris
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
