On Tue, Mar 20, 2018 at 3:11 PM, Samuel Pitoiset
<samuel.pitoi...@gmail.com> wrote:
> Ported from AMVDVLK.
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
> ---
> src/amd/vulkan/radv_pipeline.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index 89c5e69941..638c3074ec 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -2198,9 +2198,11 @@ radv_pipeline_generate_depth_stencil_state(struct
> radeon_winsys_cs *cs,
> const VkPipelineDepthStencilStateCreateInfo *vkds =
> pCreateInfo->pDepthStencilState;
> RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
> struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
> + struct radv_shader_variant *ps =
> pipeline->shaders[MESA_SHADER_FRAGMENT];
> struct radv_render_pass_attachment *attachment = NULL;
> uint32_t db_depth_control = 0, db_stencil_control = 0;
> uint32_t db_render_control = 0, db_render_override2 = 0;
> + uint32_t db_render_override = 0;
>
> if (subpass->depth_stencil_attachment.attachment !=
> VK_ATTACHMENT_UNUSED)
> attachment = pass->attachments +
> subpass->depth_stencil_attachment.attachment;
> @@ -2242,10 +2244,22 @@ radv_pipeline_generate_depth_stencil_state(struct
> radeon_winsys_cs *cs,
> db_render_override2 |=
> S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
> }
>
> + db_render_override |=
> S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
> +
> S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
> +
> + if (!pCreateInfo->pRasterizationState->depthClampEnable &&
> + ps->info.info.ps.writes_z) {
> + /* Optimized path when depth clamp is disabled, ported from
> + * AMDVLK.
> + */
> + db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
Is this correct when depth_range_unrestricted is *not* enabled? I
thought without a clamp we were supposed to clamp everything
implicitly to [0,1].
> + }
> +
> radeon_set_context_reg(cs, R_028800_DB_DEPTH_CONTROL,
> db_depth_control);
> radeon_set_context_reg(cs, R_02842C_DB_STENCIL_CONTROL,
> db_stencil_control);
>
> radeon_set_context_reg(cs, R_028000_DB_RENDER_CONTROL,
> db_render_control);
> + radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE,
> db_render_override);
> radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
> db_render_override2);
> }
>
> --
> 2.16.2
>
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