Otherwise the specified surface state will allow the GPU to access
memory up to BufferOffset bytes past the end of the buffer. Found by
inspection.
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index ed4def9046e..2ab15af793a 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -654,7 +654,8 @@ buffer_texture_range_size(struct brw_context *brw,
* so that when ISL divides by stride to obtain the number of texels, that
* texel count is clamped to MAX_TEXTURE_BUFFER_SIZE.
*/
- return MIN3((unsigned)obj->BufferSize, buffer_size,
+ return MIN3((unsigned)obj->BufferSize,
+ buffer_size - obj->BufferOffset,
brw->ctx.Const.MaxTextureBufferSize * texel_size);
}
--
2.16.1
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