On Fri, Feb 23, 2018 at 5:18 AM, Thierry Reding <thierry.red...@gmail.com> wrote: > From: Thierry Reding <tred...@nvidia.com> > > The disk cache implementation uses 64-bit atomic operations. For some > architectures, such as 32-bit ARM, GCC will not be able to translate > these operations into lock-free instructions and will instead rely on
Here, and in the comment in meson.build, I think you mean "atomic" rather than "lock-free" instructions? It's at least confusing, since on x86 atomic instructions have a "lock" prefix. Otherwise: Acked-by: Matt Turner <matts...@gmail.com> _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
