On Sun, Jan 7, 2018 at 3:42 PM, Karol Herbst <kher...@redhat.com> wrote: > significant changes to last series: > * disable support for 64 bit types > * fix tessellation shader bugs > * assume vec4 elements for variable index arrays (MemoryOpts workaround) > > piglit run -x glx -x egl -x streaming-texture-leak -x max-texture-size > tests/gpu.py: > [26010/26010] skip: 10410, pass: 15386, warn: 9, fail: 191, crash: 14 > > remaining issues: > * transform feedback with geometry shaders > * indirects in image_load/store > * interpolateAt > * getting 64 bit types to work. This is mainly limited by codegen RA being > not able to handle those correctly, because from_TGSI just generates merge > and splits and doesn't hit the faulty paths.
Just curious... what's the issue with register allocation? > > Karol Herbst (30): > nir: fix st_nir_assign_var_locations for patch variables > nvir: print the shader type when dumping headers > nvir: move common converter code in base class > nvc0: add support for NIR > nvc0/debug: add env var to make nir default > nvir/nir: run some passes to make the conversion easier > nvir/nir: track defs and provide easy access functions > nvir/nir: add nir type helper functions > nvir/nir: run assignSlots > nvir/nir: parse NIR shader info > nvir/nir: implement CFG handling > nvir/nir: implement nir_load_const_instr > nvir/nir: add skeleton for nir_intrinsic_instr > nvir/nir: implement nir_alu_instr handling > nvir/nir: implement nir_intrinsic_load_uniform > nvir/nir: implement nir_intrinsic_store_(per_vertex_)output > nvir/nir: implement nir_intrinsic_load_input > nvir/nir: implement intrinsic_discard(_if) > nvir/nir: implement loading system values > nvir/nir: implement nir_ssa_undef_instr > nvir/nir: implement nir_instr_type_tex > nvir/nir: add getOperation for intrinsics > nvir/nir: implement vote and ballot > nvir/nir: implement variable indexing > nvir/nir: implement geometry shader nir_intrinsics > nvir/nir: implement nir_intrinsic_load_ubo > nvir/nir: implement ssbo intrinsics > nvir/nir: implement images > nvir/nir: add memory barriers > nvir/nir: implement load_per_vertex_output > > src/gallium/drivers/nouveau/Makefile.sources | 3 + > src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 3 + > src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 + > .../nouveau/codegen/nv50_ir_from_common.cpp | 107 + > .../drivers/nouveau/codegen/nv50_ir_from_common.h | 58 + > .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 2716 > ++++++++++++++++++++ > .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 106 +- > src/gallium/drivers/nouveau/meson.build | 12 +- > src/gallium/drivers/nouveau/nouveau_screen.c | 4 + > src/gallium/drivers/nouveau/nouveau_screen.h | 2 + > src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 19 +- > src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 57 +- > src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 27 +- > src/mesa/state_tracker/st_glsl_to_nir.cpp | 8 +- > 14 files changed, 3003 insertions(+), 120 deletions(-) > create mode 100644 > src/gallium/drivers/nouveau/codegen/nv50_ir_from_common.cpp > create mode 100644 src/gallium/drivers/nouveau/codegen/nv50_ir_from_common.h > create mode 100644 src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp > > -- > 2.14.3 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
