Zhang, Boyuan wrote:
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 5170c67..c6dc420 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -362,6 +362,233 @@ static void radeon_enc_quality_params(struct
radeon_encoder *enc)
RADEON_ENC_END();
}
+static void radeon_enc_nalu_sps(struct radeon_encoder *enc) {
+ RADEON_ENC_BEGIN(RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU);
+ RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
+ uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++];
+ radeon_enc_reset(enc);
+ radeon_enc_set_emulation_prevention(enc, false);
+ radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
+ radeon_enc_code_fixed_bits(enc, 0x67, 8);
+ radeon_enc_byte_align(enc);
+ radeon_enc_set_emulation_prevention(enc, true);
+ radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8);
+ radeon_enc_code_fixed_bits(enc, 0x04, 8);
Please always set constraint_set1_flag when profile_idc is 66. There are
enough actually-constrained-baseline-but-not-marked-as-such streams in the
world already to catch out decoders without full baseline support (that is, all
of them).
Also, "constraint_set5_flag shall be equal to 0 when profile_idc is not equal to 77,
88, 100, or 118".
[Boyuan] Thanks for pointing out. I modified the value to be 0x44 in the new
patch (set1=1, and set5=1) since we only support constrained baseline for now.
It's not really with cabac though. I know there was a patch to turn it
off - but that would have been wasteful and make linux < windows.
Why not use 77 if cabac is on + not set constrained bits, windows seems
to set main.
Currently with vce trying to set main manually from ffmeg/gst in order
to get something "correct" still sets flags = something that's not seen
as main (but works).
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