On Thu, Oct 26, 2017 at 7:23 PM, Eric Anholt <e...@anholt.net> wrote: > Marek Olšák <mar...@gmail.com> writes: > >> From: Marek Olšák <marek.ol...@amd.com> > > Could you hit vc5, as well? > > I'm not clear on why this is a pipe_cap instead of just updating type or > comments on the pipe structs to say what the new behavior is -- aren't > most of us using 32-bit math that will wrap the same on addition?
r300 and r600 have a command buffer checker in the kernel that expects unsigned relative offsets. For radeonsi, there is a requirement that: - the virtual 40-bit or 48-bit GPU address doesn't under-wrap - shader buffer slots have a "max size" field that shouldn't wrap (a negative offset increases the max size) We also lose hw bounds checking (address clamping) for the memory range preceding the beginning of the buffer. Since this can have non-trivial consequences for various drivers, I can enable the CAP on request only. Marek _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
