SaschaWillems Vulkan demo tessellation:
~4300fps -> ~4800fps
---
src/amd/vulkan/radv_pipeline.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index d0e47383d7..69bda152e2 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1760,20 +1760,21 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
}
if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
nir_builder fs_b;
nir_builder_init_simple_shader(&fs_b, NULL,
MESA_SHADER_FRAGMENT, NULL);
fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
fs_m.nir = fs_b.shader;
modules[MESA_SHADER_FRAGMENT] = &fs_m;
}
+ int prev = -1;
for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
const VkPipelineShaderStageCreateInfo *stage = pStages[i];
if (!modules[i])
continue;
nir[i] = radv_shader_compile_to_nir(device, modules[i],
stage ? stage->pName :
"main", i,
stage ?
stage->pSpecializationInfo : NULL);
pipeline->active_stages |= mesa_to_vk_shader_stage(i);
@@ -1790,20 +1791,32 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
if (i != first)
mask = mask | nir_var_shader_in;
if (i != last)
mask = mask | nir_var_shader_out;
nir_lower_io_to_scalar_early(nir[i], mask);
radv_optimize_nir(nir[i]);
}
+
+ if (prev != -1) {
+ nir_compact_varyings(nir[prev], nir[i], true);
+
+ /* TODO: In future nir_compact_varyings() should update
the varying
+ * input/output mask to reflect the packing it has just
done. However
+ * until we have an array/matrix splitting pass we
would just be
+ * duplicating the complex partial marking code in
nir_gather_info().
+ */
+ nir_shader_gather_info(nir[i],
nir_shader_get_entrypoint(nir[i]));
+ }
+ prev = i;
}
if (nir[MESA_SHADER_TESS_CTRL]) {
/* TODO: This is no longer used as a key we should refactor
this */
if (keys)
keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode =
nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors =
!!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER));
nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL],
nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
}
--
2.13.6
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