From: Nicolai Hähnle <nicolai.haeh...@amd.com>
v2: rebase fixes
---
src/gallium/drivers/radeon/r600_pipe_common.c | 4 ----
src/gallium/drivers/radeon/r600_pipe_common.h | 1 -
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state_draw.c | 10 +++++-----
src/gallium/drivers/radeonsi/si_state_shaders.c | 8 ++++----
src/gallium/drivers/radeonsi/si_viewport.c | 2 +-
6 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index d50982b8636..1aceb5b7559 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -717,24 +717,20 @@ bool si_common_context_init(struct r600_common_context
*rctx,
rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
rctx->b.texture_subdata = u_default_texture_subdata;
rctx->b.memory_barrier = r600_memory_barrier;
rctx->b.flush = r600_flush_from_st;
rctx->b.set_debug_callback = r600_set_debug_callback;
rctx->b.fence_server_sync = r600_fence_server_sync;
rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
rctx->b.buffer_subdata = si_buffer_subdata;
- /* Set a reasonable default to avoid a performance regression in r600
- * on stable branches. */
- rctx->current_rast_prim = PIPE_PRIM_TRIANGLES;
-
if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
rctx->b.get_device_reset_status = r600_get_reset_status;
rctx->gpu_reset_counter =
rctx->ws->query_value(rctx->ws,
RADEON_GPU_RESET_COUNTER);
}
rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
si_init_context_texture_functions(rctx);
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 1558943bfec..597ff0280e0 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -564,21 +564,20 @@ struct r600_common_context {
/* Current unaccounted memory usage. */
uint64_t vram;
uint64_t gtt;
/* States. */
struct r600_streamout streamout;
/* Additional context states. */
unsigned flags; /* flush flags */
- enum pipe_prim_type current_rast_prim; /* primitive type
after TES, GS */
/* Queries. */
/* Maintain the list of active queries for pausing between IBs. */
int num_occlusion_queries;
int num_perfect_occlusion_queries;
struct list_head active_queries;
unsigned num_cs_dw_queries_suspend;
/* Misc stats. */
unsigned num_draw_calls;
unsigned num_decompress_calls;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index b3d5b186457..e0759eddb2c 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -426,20 +426,21 @@ struct si_context {
int last_sh_base_reg;
int last_primitive_restart_en;
int last_restart_index;
int last_gs_out_prim;
int last_prim;
int last_multi_vgt_param;
int last_rast_prim;
unsigned last_sc_line_stipple;
unsigned current_vs_state;
unsigned last_vs_state;
+ enum pipe_prim_type current_rast_prim; /* primitive type after TES,
GS */
/* Scratch buffer */
struct r600_atom scratch_state;
struct r600_resource *scratch_buffer;
unsigned scratch_waves;
unsigned spi_tmpring_size;
struct r600_resource *compute_scratch_buffer;
/* Emitted derived tessellation state. */
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 9a6c9c8f842..2d4c9c5b9f3 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -524,21 +524,21 @@ static unsigned si_get_ia_multi_vgt_param(struct
si_context *sctx,
sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
}
return ia_multi_vgt_param;
}
/* rast_prim is the primitive type after GS. */
static void si_emit_rasterizer_prim_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
- enum pipe_prim_type rast_prim = sctx->b.current_rast_prim;
+ enum pipe_prim_type rast_prim = sctx->current_rast_prim;
struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
/* Skip this if not rendering lines. */
if (rast_prim != PIPE_PRIM_LINES &&
rast_prim != PIPE_PRIM_LINE_LOOP &&
rast_prim != PIPE_PRIM_LINE_STRIP &&
rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
return;
@@ -574,21 +574,21 @@ static void si_emit_vs_state(struct si_context *sctx,
sctx->last_vs_state = sctx->current_vs_state;
}
}
static void si_emit_draw_registers(struct si_context *sctx,
const struct pipe_draw_info *info,
unsigned num_patches)
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
unsigned prim = si_conv_pipe_prim(info->mode);
- unsigned gs_out_prim =
si_conv_prim_to_gs_out(sctx->b.current_rast_prim);
+ unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
unsigned ia_multi_vgt_param;
ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
/* Draw state. */
if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
if (sctx->b.chip_class >= GFX9)
radeon_set_uconfig_reg_idx(cs,
R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
else if (sctx->b.chip_class >= CIK)
radeon_set_context_reg_idx(cs,
R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
@@ -1250,29 +1250,29 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
if (sctx->gs_shader.cso)
rast_prim = sctx->gs_shader.cso->gs_output_prim;
else if (sctx->tes_shader.cso) {
if
(sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
rast_prim = PIPE_PRIM_POINTS;
else
rast_prim =
sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
} else
rast_prim = info->mode;
- if (rast_prim != sctx->b.current_rast_prim) {
- bool old_is_poly = sctx->b.current_rast_prim >=
PIPE_PRIM_TRIANGLES;
+ if (rast_prim != sctx->current_rast_prim) {
+ bool old_is_poly = sctx->current_rast_prim >=
PIPE_PRIM_TRIANGLES;
bool new_is_poly = rast_prim >= PIPE_PRIM_TRIANGLES;
if (old_is_poly != new_is_poly) {
sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
si_mark_atom_dirty(sctx, &sctx->scissors.atom);
}
- sctx->b.current_rast_prim = rast_prim;
+ sctx->current_rast_prim = rast_prim;
sctx->do_update_shaders = true;
}
if (sctx->tes_shader.cso &&
(sctx->b.family == CHIP_VEGA10 || sctx->b.family == CHIP_RAVEN)) {
/* Determine whether the LS VGPR fix should be applied.
*
* It is only required when num input CPs > num output CPs,
* which cannot happen with the fixed function TCS. We should
* also update this bit when switching from TCS to fixed
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 42814d9fd58..7619e2f04aa 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1401,24 +1401,24 @@ static inline void si_shader_selector_key(struct
pipe_context *ctx,
}
/* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't
enabled). */
if (!key->part.ps.epilog.last_cbuf) {
key->part.ps.epilog.spi_shader_col_format &=
sel->colors_written_4bit;
key->part.ps.epilog.color_is_int8 &=
sel->info.colors_written;
key->part.ps.epilog.color_is_int10 &=
sel->info.colors_written;
}
if (rs) {
- bool is_poly = (sctx->b.current_rast_prim >=
PIPE_PRIM_TRIANGLES &&
- sctx->b.current_rast_prim <=
PIPE_PRIM_POLYGON) ||
- sctx->b.current_rast_prim >=
PIPE_PRIM_TRIANGLES_ADJACENCY;
- bool is_line = !is_poly && sctx->b.current_rast_prim !=
PIPE_PRIM_POINTS;
+ bool is_poly = (sctx->current_rast_prim >=
PIPE_PRIM_TRIANGLES &&
+ sctx->current_rast_prim <=
PIPE_PRIM_POLYGON) ||
+ sctx->current_rast_prim >=
PIPE_PRIM_TRIANGLES_ADJACENCY;
+ bool is_line = !is_poly && sctx->current_rast_prim !=
PIPE_PRIM_POINTS;
key->part.ps.prolog.color_two_side = rs->two_side &&
sel->info.colors_read;
key->part.ps.prolog.flatshade_colors = rs->flatshade &&
sel->info.colors_read;
if (sctx->queued.named.blend) {
key->part.ps.epilog.alpha_to_one =
sctx->queued.named.blend->alpha_to_one &&
rs->multisample_enable;
}
key->part.ps.prolog.poly_stipple =
rs->poly_stipple_enable && is_poly;
diff --git a/src/gallium/drivers/radeonsi/si_viewport.c
b/src/gallium/drivers/radeonsi/si_viewport.c
index fcc869f1622..2d8b182ace0 100644
--- a/src/gallium/drivers/radeonsi/si_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_viewport.c
@@ -180,21 +180,21 @@ static void si_emit_guardband(struct si_context *ctx,
bottom = ( max_range - vp.translate[1]) / vp.scale[1];
assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
guardband_x = MIN2(-left, right);
guardband_y = MIN2(-top, bottom);
discard_x = 1.0;
discard_y = 1.0;
- if (ctx->b.current_rast_prim < PIPE_PRIM_TRIANGLES) {
+ if (ctx->current_rast_prim < PIPE_PRIM_TRIANGLES) {
/* When rendering wide points or lines, we need to be more
* conservative about when to discard them entirely. Since
* point size can be determined by the VS output, we basically
* disable discard completely completely here.
*
* TODO: This can hurt performance when rendering lines and
* points with fixed size, and could be improved.
*/
discard_x = guardband_x;
discard_y = guardband_y;
--
2.11.0
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