For patches 2-11:
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Patch 1:
Acked-by: Marek Olšák <marek.ol...@amd.com>
Marek
On Sat, Sep 16, 2017 at 1:23 PM, Nicolai Hähnle <nhaeh...@gmail.com> wrote:
> From: Nicolai Hähnle <nicolai.haeh...@amd.com>
>
> Note: this causes spurious regressions in some current piglit tests,
> because the tests incorrectly assume that there is no denorm support for
> doubles. I'm going to send out a fix for those tests as well.
> ---
> src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
> src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 25
> +++++++++++++++++++++++
> 2 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
> b/src/gallium/drivers/radeonsi/si_pipe.c
> index 114969d47a5..531e6148553 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -739,40 +739,40 @@ static int si_get_shader_param(struct pipe_screen*
> pscreen,
> case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
> case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
> case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
> case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
> case PIPE_SHADER_CAP_INTEGERS:
> case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
> case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
> case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
> case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
> case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
> + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
> return 1;
>
> case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
> /* TODO: Indirect indexing of GS inputs is unimplemented. */
> return shader != PIPE_SHADER_GEOMETRY &&
> (sscreen->llvm_has_working_vgpr_indexing ||
> /* TCS and TES load inputs directly from LDS or
> * offchip memory, so indirect indexing is trivial. */
> shader == PIPE_SHADER_TESS_CTRL ||
> shader == PIPE_SHADER_TESS_EVAL);
>
> case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
> return sscreen->llvm_has_working_vgpr_indexing ||
> /* TCS stores outputs directly to memory. */
> shader == PIPE_SHADER_TESS_CTRL;
>
> /* Unsupported boolean features. */
> case PIPE_SHADER_CAP_SUBROUTINES:
> case PIPE_SHADER_CAP_SUPPORTED_IRS:
> - case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
> return 0;
> }
> return 0;
> }
>
> static const struct nir_shader_compiler_options nir_options = {
> .vertex_id_zero_based = true,
> .lower_scmp = true,
> .lower_flrp32 = true,
> .lower_fsat = true,
> diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
> b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
> index ba7ec4f4107..818ca499d90 100644
> --- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
> +++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
> @@ -727,20 +727,41 @@ static void emit_rsq(const struct lp_build_tgsi_action
> *action,
> {
> LLVMValueRef sqrt =
> lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_SQRT,
> emit_data->args[0]);
>
> emit_data->output[emit_data->chan] =
> lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_DIV,
> bld_base->base.one, sqrt);
> }
>
> +static void dfracexp_fetch_args(struct lp_build_tgsi_context *bld_base,
> + struct lp_build_emit_data *emit_data)
> +{
> + emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
> 0, TGSI_CHAN_X);
> + emit_data->arg_count = 1;
> +}
> +
> +static void dfracexp_emit(const struct lp_build_tgsi_action *action,
> + struct lp_build_tgsi_context *bld_base,
> + struct lp_build_emit_data *emit_data)
> +{
> + struct si_shader_context *ctx = si_shader_context(bld_base);
> +
> + emit_data->output[emit_data->chan] =
> + lp_build_intrinsic(ctx->ac.builder,
> "llvm.amdgcn.frexp.mant.f64",
> + ctx->ac.f64, &emit_data->args[0], 1, 0);
> + emit_data->output1[emit_data->chan] =
> + lp_build_intrinsic(ctx->ac.builder,
> "llvm.amdgcn.frexp.exp.i32.f64",
> + ctx->ac.i32, &emit_data->args[0], 1, 0);
> +}
> +
> void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base)
> {
> lp_set_default_actions(bld_base);
>
> bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
> bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
> bld_base->op_actions[TGSI_OPCODE_BFI].emit = emit_bfi;
> bld_base->op_actions[TGSI_OPCODE_BREV].emit =
> build_tgsi_intrinsic_nomem;
> bld_base->op_actions[TGSI_OPCODE_BREV].intr_name =
> "llvm.bitreverse.i32";
> bld_base->op_actions[TGSI_OPCODE_CEIL].emit =
> build_tgsi_intrinsic_nomem;
> @@ -765,20 +786,24 @@ void si_shader_context_init_alu(struct
> lp_build_tgsi_context *bld_base)
> bld_base->op_actions[TGSI_OPCODE_DSGE].emit = emit_dcmp;
> bld_base->op_actions[TGSI_OPCODE_DSLT].emit = emit_dcmp;
> bld_base->op_actions[TGSI_OPCODE_DSNE].emit = emit_dcmp;
> bld_base->op_actions[TGSI_OPCODE_DSSG].emit = emit_ssg;
> bld_base->op_actions[TGSI_OPCODE_DRSQ].emit =
> build_tgsi_intrinsic_nomem;
> bld_base->op_actions[TGSI_OPCODE_DRSQ].intr_name =
> "llvm.amdgcn.rsq.f64";
> bld_base->op_actions[TGSI_OPCODE_DSQRT].emit =
> build_tgsi_intrinsic_nomem;
> bld_base->op_actions[TGSI_OPCODE_DSQRT].intr_name = "llvm.sqrt.f64";
> bld_base->op_actions[TGSI_OPCODE_DTRUNC].emit =
> build_tgsi_intrinsic_nomem;
> bld_base->op_actions[TGSI_OPCODE_DTRUNC].intr_name = "llvm.trunc.f64";
> + bld_base->op_actions[TGSI_OPCODE_DFRACEXP].fetch_args =
> dfracexp_fetch_args;
> + bld_base->op_actions[TGSI_OPCODE_DFRACEXP].emit = dfracexp_emit;
> + bld_base->op_actions[TGSI_OPCODE_DLDEXP].emit =
> build_tgsi_intrinsic_nomem;
> + bld_base->op_actions[TGSI_OPCODE_DLDEXP].intr_name =
> "llvm.amdgcn.ldexp.f64";
> bld_base->op_actions[TGSI_OPCODE_EX2].emit =
> build_tgsi_intrinsic_nomem;
> bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.exp2.f32";
> bld_base->op_actions[TGSI_OPCODE_FLR].emit =
> build_tgsi_intrinsic_nomem;
> bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "llvm.floor.f32";
> bld_base->op_actions[TGSI_OPCODE_FMA].emit =
> bld_base->op_actions[TGSI_OPCODE_MAD].emit;
> bld_base->op_actions[TGSI_OPCODE_FRC].emit = emit_frac;
> bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
> bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
> bld_base->op_actions[TGSI_OPCODE_FSEQ].emit = emit_fcmp;
> --
> 2.11.0
>
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