From: Nicolai Hähnle <nicolai.haeh...@amd.com>
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi.c | 2 +-
src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c | 4 ++--
src/gallium/auxiliary/tgsi/tgsi_info.c | 5 ++++-
src/gallium/auxiliary/tgsi/tgsi_info.h | 2 +-
src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 2 +-
5 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
index b33976bb647..079a6eed496 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
@@ -194,21 +194,21 @@ void lp_build_fetch_args(
* - if src is 64-bit then src == dst.
* - else for f2d, d.xy = s.x
* - else for f2d, d.zw = s.y
* 3. if dst is single, src is 64-bit
* - map dst x,z to src xy;
* - map dst y,w to src zw;
*/
static int get_src_chan_idx(unsigned opcode,
int dst_chan_index)
{
- enum tgsi_opcode_type dtype = tgsi_opcode_infer_dst_type(opcode);
+ enum tgsi_opcode_type dtype = tgsi_opcode_infer_dst_type(opcode, 0);
enum tgsi_opcode_type stype = tgsi_opcode_infer_src_type(opcode, 0);
if (!tgsi_type_is_64bit(dtype) && !tgsi_type_is_64bit(stype))
return dst_chan_index;
if (tgsi_type_is_64bit(dtype)) {
if (dst_chan_index == 1 || dst_chan_index == 3)
return -1;
if (tgsi_type_is_64bit(stype))
return dst_chan_index;
if (dst_chan_index == 0)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index 45110e8b9fe..ca7e605792e 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -1744,21 +1744,21 @@ emit_store_chan(
unsigned chan_index,
LLVMValueRef value)
{
struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
const struct tgsi_full_dst_register *reg = &inst->Dst[index];
struct lp_build_context *float_bld = &bld_base->base;
struct lp_build_context *int_bld = &bld_base->int_bld;
LLVMValueRef indirect_index = NULL;
- enum tgsi_opcode_type dtype =
tgsi_opcode_infer_dst_type(inst->Instruction.Opcode);
+ enum tgsi_opcode_type dtype =
tgsi_opcode_infer_dst_type(inst->Instruction.Opcode, index);
/*
* Apply saturation.
*
* It is always assumed to be float.
*/
if (inst->Instruction.Saturate) {
assert(dtype == TGSI_TYPE_FLOAT ||
dtype == TGSI_TYPE_UNTYPED);
value = LLVMBuildBitCast(builder, value, float_bld->vec_type, "");
@@ -1910,21 +1910,21 @@ emit_debug(
static void
emit_store(
struct lp_build_tgsi_context * bld_base,
const struct tgsi_full_instruction * inst,
const struct tgsi_opcode_info * info,
unsigned index,
LLVMValueRef dst[4])
{
- enum tgsi_opcode_type dtype =
tgsi_opcode_infer_dst_type(inst->Instruction.Opcode);
+ enum tgsi_opcode_type dtype =
tgsi_opcode_infer_dst_type(inst->Instruction.Opcode, index);
unsigned writemask = inst->Dst[index].Register.WriteMask;
while (writemask) {
unsigned chan_index = u_bit_scan(&writemask);
if (tgsi_type_is_64bit(dtype) && (chan_index == 1 || chan_index == 3))
continue;
emit_store_chan(bld_base, inst, index, chan_index, dst[chan_index]);
}
}
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c
b/src/gallium/auxiliary/tgsi/tgsi_info.c
index 36be463dc84..62b41c031b3 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -305,14 +305,17 @@ tgsi_opcode_infer_src_type(uint opcode, uint src_idx)
return TGSI_TYPE_SIGNED64;
default:
return tgsi_opcode_infer_type(opcode);
}
}
/*
* infer the destination type of a TGSI opcode.
*/
enum tgsi_opcode_type
-tgsi_opcode_infer_dst_type( uint opcode )
+tgsi_opcode_infer_dst_type( uint opcode, uint dst_idx )
{
+ if (dst_idx == 1 && opcode == TGSI_OPCODE_DFRACEXP)
+ return TGSI_TYPE_SIGNED;
+
return tgsi_opcode_infer_type(opcode);
}
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.h
b/src/gallium/auxiliary/tgsi/tgsi_info.h
index f3ef46fb4a8..8d32f4774be 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.h
@@ -107,17 +107,17 @@ static inline bool tgsi_type_is_64bit(enum
tgsi_opcode_type type)
if (type == TGSI_TYPE_DOUBLE || type == TGSI_TYPE_UNSIGNED64 ||
type == TGSI_TYPE_SIGNED64)
return true;
return false;
}
enum tgsi_opcode_type
tgsi_opcode_infer_src_type( uint opcode, uint src_idx );
enum tgsi_opcode_type
-tgsi_opcode_infer_dst_type( uint opcode );
+tgsi_opcode_infer_dst_type( uint opcode, uint dst_idx );
#if defined __cplusplus
}
#endif
#endif /* TGSI_INFO_H */
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index 67172729bb6..1a8f8315972 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -883,21 +883,21 @@ void si_llvm_emit_store(struct lp_build_tgsi_context
*bld_base,
const struct tgsi_opcode_info *info,
unsigned index,
LLVMValueRef dst[4])
{
struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = &ctx->gallivm;
const struct tgsi_full_dst_register *reg = &inst->Dst[index];
LLVMBuilderRef builder = ctx->gallivm.builder;
LLVMValueRef temp_ptr, temp_ptr2 = NULL;
bool is_vec_store = false;
- enum tgsi_opcode_type dtype =
tgsi_opcode_infer_dst_type(inst->Instruction.Opcode);
+ enum tgsi_opcode_type dtype =
tgsi_opcode_infer_dst_type(inst->Instruction.Opcode, index);
if (dst[0]) {
LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0]));
is_vec_store = (k == LLVMVectorTypeKind);
}
if (is_vec_store) {
LLVMValueRef values[4] = {};
uint32_t writemask = reg->Register.WriteMask;
while (writemask) {
--
2.11.0
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