From: Nicolai Hähnle <nicolai.haeh...@amd.com>
v2: update for LLVMValueRefs in ac_shader_abi
---
src/amd/common/ac_nir_to_llvm.c | 30 +++++++++++++++++-------------
src/amd/common/ac_shader_abi.h | 1 +
src/gallium/drivers/radeonsi/si_shader.c | 12 ++++++++----
3 files changed, 26 insertions(+), 17 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 0cd3590..f8eb0c9 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -121,21 +121,20 @@ struct nir_to_llvm_context {
LLVMValueRef esgs_ring;
LLVMValueRef gsvs_ring;
LLVMValueRef hs_ring_tess_offchip;
LLVMValueRef hs_ring_tess_factor;
LLVMValueRef prim_mask;
LLVMValueRef sample_pos_offset;
LLVMValueRef persp_sample, persp_center, persp_centroid;
LLVMValueRef linear_sample, linear_center, linear_centroid;
- LLVMValueRef frag_pos[4];
LLVMTypeRef i1;
LLVMTypeRef i8;
LLVMTypeRef i16;
LLVMTypeRef i32;
LLVMTypeRef i64;
LLVMTypeRef v2i32;
LLVMTypeRef v3i32;
LLVMTypeRef v4i32;
LLVMTypeRef v8i32;
@@ -816,24 +815,24 @@ static void create_function(struct nir_to_llvm_context
*ctx)
add_user_sgpr_argument(&args, ctx->i32,
&ctx->sample_pos_offset); /* sample position offset */
add_sgpr_argument(&args, ctx->i32, &ctx->prim_mask); /* prim
mask */
add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_sample); /*
persp sample */
add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_center); /*
persp center */
add_vgpr_argument(&args, ctx->v2i32, &ctx->persp_centroid); /*
persp centroid */
add_vgpr_argument(&args, ctx->v3i32, NULL); /* persp pull model
*/
add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_sample); /*
linear sample */
add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_center); /*
linear center */
add_vgpr_argument(&args, ctx->v2i32, &ctx->linear_centroid); /*
linear centroid */
add_vgpr_argument(&args, ctx->f32, NULL); /* line stipple tex
*/
- add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[0]); /* pos
x float */
- add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[1]); /* pos
y float */
- add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[2]); /* pos
z float */
- add_vgpr_argument(&args, ctx->f32, &ctx->frag_pos[3]); /* pos
w float */
+ add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[0]); /*
pos x float */
+ add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[1]); /*
pos y float */
+ add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[2]); /*
pos z float */
+ add_vgpr_argument(&args, ctx->f32, &ctx->abi.frag_pos[3]); /*
pos w float */
add_vgpr_argument(&args, ctx->i32, &ctx->abi.front_face); /*
front face */
add_vgpr_argument(&args, ctx->i32, &ctx->abi.ancillary); /*
ancillary */
add_vgpr_argument(&args, ctx->i32, &ctx->abi.sample_coverage);
/* sample coverage */
add_vgpr_argument(&args, ctx->i32, NULL); /* fixed pt */
break;
default:
unreachable("Shader stage not implemented");
}
ctx->main_function = create_llvm_function(
@@ -3278,21 +3277,24 @@ static LLVMValueRef get_image_coords(struct
ac_nir_context *ctx,
int chan;
fmask_load_address[0] =
LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
fmask_load_address[1] =
LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
if (glsl_sampler_type_is_array(type))
fmask_load_address[2] =
LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
else
fmask_load_address[2] = NULL;
if (add_frag_pos) {
for (chan = 0; chan < 2; ++chan)
- fmask_load_address[chan] =
LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
LLVMBuildFPToUI(ctx->ac.builder, ctx->nctx->frag_pos[chan], ctx->ac.i32, ""),
"");
+ fmask_load_address[chan] =
+ LLVMBuildAdd(ctx->ac.builder,
fmask_load_address[chan],
+
LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
+ ctx->ac.i32,
""), "");
}
sample_index = adjust_sample_index_using_fmask(&ctx->ac,
fmask_load_address[0],
fmask_load_address[1],
fmask_load_address[2],
sample_index,
get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, true, false));
}
if (count == 1) {
if (instr->src[0].ssa->num_components)
@@ -3302,21 +3304,22 @@ static LLVMValueRef get_image_coords(struct
ac_nir_context *ctx,
} else {
int chan;
if (is_ms)
count--;
for (chan = 0; chan < count; ++chan) {
coords[chan] = LLVMBuildExtractElement(ctx->ac.builder,
src0, masks[chan], "");
}
if (add_frag_pos) {
for (chan = 0; chan < count; ++chan)
- coords[chan] = LLVMBuildAdd(ctx->ac.builder,
coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->nctx->frag_pos[chan],
ctx->ac.i32, ""), "");
+ coords[chan] = LLVMBuildAdd(ctx->ac.builder,
coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
+ ctx->ac.i32, ""), "");
}
if (is_ms) {
coords[count] = sample_index;
count++;
}
if (count == 3) {
coords[3] = LLVMGetUndef(ctx->ac.i32);
count = 4;
}
@@ -3712,26 +3715,26 @@ static LLVMValueRef load_sample_position(struct
nir_to_llvm_context *ctx,
ptr = LLVMBuildBitCast(ctx->builder, ptr,
const_array(ctx->v2f32, 64), "");
sample_id = LLVMBuildAdd(ctx->builder, sample_id,
ctx->sample_pos_offset, "");
result = ac_build_indexed_load(&ctx->ac, ptr, sample_id, false);
return result;
}
-static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
+static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
{
LLVMValueRef values[2];
- values[0] = emit_ffract(&ctx->ac, ctx->frag_pos[0]);
- values[1] = emit_ffract(&ctx->ac, ctx->frag_pos[1]);
+ values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0]);
+ values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1]);
return ac_build_gather_values(&ctx->ac, values, 2);
}
static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
const nir_intrinsic_instr *instr)
{
LLVMValueRef result[2];
LLVMValueRef interp_param, attr_number;
unsigned location;
unsigned chan;
@@ -3971,21 +3974,21 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
} else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
ctx->nctx->shader_info->tcs.uses_prim_id = true;
result = ctx->nctx->tes_patch_id;
} else
fprintf(stderr, "Unknown primitive id intrinsic: %d",
ctx->stage);
break;
case nir_intrinsic_load_sample_id:
result = unpack_param(ctx->nctx, ctx->abi->ancillary, 8, 4);
break;
case nir_intrinsic_load_sample_pos:
- result = load_sample_pos(ctx->nctx);
+ result = load_sample_pos(ctx);
break;
case nir_intrinsic_load_sample_mask_in:
result = ctx->abi->sample_coverage;
break;
case nir_intrinsic_load_front_face:
result = ctx->abi->front_face;
break;
case nir_intrinsic_load_instance_id:
result = ctx->abi->instance_id;
break;
@@ -4978,23 +4981,24 @@ handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
interp_param = *inputs;
interp_fs_input(ctx, index, interp_param,
ctx->prim_mask,
inputs);
if (!interp_param)
ctx->shader_info->fs.flat_shaded_mask |= 1u <<
index;
++index;
} else if (i == VARYING_SLOT_POS) {
for(int i = 0; i < 3; ++i)
- inputs[i] = ctx->frag_pos[i];
+ inputs[i] = ctx->abi.frag_pos[i];
- inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one,
ctx->frag_pos[3]);
+ inputs[3] = ac_build_fdiv(&ctx->ac, ctx->f32one,
+ ctx->abi.frag_pos[3]);
}
}
ctx->shader_info->fs.num_interp = index;
if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
ctx->shader_info->fs.has_pcoord = true;
if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
ctx->shader_info->fs.prim_id_input = true;
if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
ctx->shader_info->fs.layer_input = true;
ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index fd62f22..c2dd1c3 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -37,20 +37,21 @@ enum ac_descriptor_type {
* radv to share a compiler backend.
*/
struct ac_shader_abi {
enum chip_class chip_class;
LLVMValueRef base_vertex;
LLVMValueRef start_instance;
LLVMValueRef draw_id;
LLVMValueRef vertex_id;
LLVMValueRef instance_id;
+ LLVMValueRef frag_pos[4];
LLVMValueRef front_face;
LLVMValueRef ancillary;
LLVMValueRef sample_coverage;
/* For VS and PS: pre-loaded shader inputs.
*
* Currently only used for NIR shaders; indexed by variables'
* driver_location.
*/
LLVMValueRef *inputs;
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 7eba137..7fa76cd 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -4505,24 +4505,28 @@ static void create_function(struct si_shader_context
*ctx)
add_arg_checked(&fninfo, ARG_SGPR, ctx->i32,
SI_PARAM_PRIM_MASK);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_PERSP_SAMPLE);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_PERSP_CENTER);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_PERSP_CENTROID);
add_arg_checked(&fninfo, ARG_VGPR, v3i32,
SI_PARAM_PERSP_PULL_MODEL);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_LINEAR_SAMPLE);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_LINEAR_CENTER);
add_arg_checked(&fninfo, ARG_VGPR, ctx->v2i32,
SI_PARAM_LINEAR_CENTROID);
add_arg_checked(&fninfo, ARG_VGPR, ctx->f32,
SI_PARAM_LINE_STIPPLE_TEX);
- add_arg_checked(&fninfo, ARG_VGPR, ctx->f32,
SI_PARAM_POS_X_FLOAT);
- add_arg_checked(&fninfo, ARG_VGPR, ctx->f32,
SI_PARAM_POS_Y_FLOAT);
- add_arg_checked(&fninfo, ARG_VGPR, ctx->f32,
SI_PARAM_POS_Z_FLOAT);
- add_arg_checked(&fninfo, ARG_VGPR, ctx->f32,
SI_PARAM_POS_W_FLOAT);
+ add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
+ &ctx->abi.frag_pos[0],
SI_PARAM_POS_X_FLOAT);
+ add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
+ &ctx->abi.frag_pos[1],
SI_PARAM_POS_Y_FLOAT);
+ add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
+ &ctx->abi.frag_pos[2],
SI_PARAM_POS_Z_FLOAT);
+ add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
+ &ctx->abi.frag_pos[3],
SI_PARAM_POS_W_FLOAT);
add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
&ctx->abi.front_face,
SI_PARAM_FRONT_FACE);
shader->info.face_vgpr_index = 20;
add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
&ctx->abi.ancillary, SI_PARAM_ANCILLARY);
add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
&ctx->abi.sample_coverage,
SI_PARAM_SAMPLE_COVERAGE);
add_arg_checked(&fninfo, ARG_VGPR, ctx->i32,
SI_PARAM_POS_FIXED_PT);
/* Color inputs from the prolog. */
--
2.9.3
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