From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_blit.c | 9 +++++++++
src/gallium/drivers/radeonsi/si_pipe.h | 7 ++++---
src/gallium/drivers/radeonsi/si_state.c | 3 ++-
3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index 8846712..86a1553 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -719,20 +719,23 @@ static void si_clear(struct pipe_context *ctx, unsigned
buffers,
if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
continue;
if (!fb->cbufs[i])
continue;
tex = (struct r600_texture *)fb->cbufs[i]->texture;
if (tex->fmask.size == 0)
tex->dirty_level_mask &= ~(1 <<
fb->cbufs[i]->u.tex.level);
}
+
+ /* si_bind_blend_state will take care of necessary re-emitting.
*/
+ sctx->framebuffer.slow_clear_srgb_enable = srgb_enable;
}
if (zstex && zstex->htile_offset &&
zsbuf->u.tex.level == 0 &&
zsbuf->u.tex.first_layer == 0 &&
zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0))
{
/* TC-compatible HTILE only supports depth clears to 0 or 1. */
if (buffers & PIPE_CLEAR_DEPTH &&
(!zstex->tc_compatible_htile ||
depth == 0 || depth == 1)) {
@@ -780,20 +783,26 @@ static void si_clear(struct pipe_context *ctx, unsigned
buffers,
zstex->depth_cleared = true;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
}
if (sctx->db_stencil_clear) {
sctx->db_stencil_clear = false;
sctx->db_stencil_disable_expclear = false;
zstex->stencil_cleared = true;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
}
+
+ if (buffers & PIPE_CLEAR_COLOR && srgb_enable) {
+ sctx->framebuffer.slow_clear_srgb_enable = 0;
+ /* This should be dirty after restoring the blend state. */
+ assert(si_is_atom_dirty(sctx, &sctx->framebuffer.atom));
+ }
}
static void si_clear_render_target(struct pipe_context *ctx,
struct pipe_surface *dst,
const union pipe_color_union *color,
unsigned dstx, unsigned dsty,
unsigned width, unsigned height,
bool render_condition_enabled)
{
struct si_context *sctx = (struct si_context *)ctx;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index eef05cf..8f79d7b 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -170,23 +170,24 @@ struct si_framebuffer {
unsigned spi_shader_col_format;
unsigned spi_shader_col_format_alpha;
unsigned spi_shader_col_format_blend;
unsigned spi_shader_col_format_blend_alpha;
ubyte nr_samples:5; /* at most 16xAA */
ubyte log_samples:3; /* at most 4 = 16xAA */
ubyte compressed_cb_mask;
ubyte color_is_int8;
ubyte color_is_int10;
ubyte dirty_cbufs;
- bool dirty_zsbuf;
- bool any_dst_linear;
- bool do_update_surf_dirtiness;
+ ubyte slow_clear_srgb_enable;
+ bool dirty_zsbuf:1;
+ bool any_dst_linear:1;
+ bool do_update_surf_dirtiness:1;
};
struct si_clip_state {
struct r600_atom atom;
struct pipe_clip_state state;
};
struct si_sample_locs {
struct r600_atom atom;
unsigned nr_samples;
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 4c81c9a..0abcd5e 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2671,21 +2671,22 @@ static void si_set_framebuffer_state(struct
pipe_context *ctx,
sctx->framebuffer.do_update_surf_dirtiness = true;
}
}
static void si_emit_framebuffer_state(struct si_context *sctx, struct
r600_atom *atom)
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
unsigned i, nr_cbufs = state->nr_cbufs;
struct si_state_blend *blend = sctx->queued.named.blend;
- ubyte srgb_enable = blend ? blend->srgb_enable : 0;
+ ubyte srgb_enable = (blend ? blend->srgb_enable : 0) |
+ sctx->framebuffer.slow_clear_srgb_enable;
struct r600_texture *tex = NULL;
struct r600_surface *cb = NULL;
unsigned cb_color_info = 0;
/* Colorbuffers. */
for (i = 0; i < nr_cbufs; i++) {
uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
unsigned cb_color_attrib;
if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
--
2.7.4
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