For preventing confusion with a radeon winsys.
Signed-off-by: Bas Nieuwenhuizen <ba...@google.com>
---
src/amd/vulkan/radv_cmd_buffer.c | 26 ++---
src/amd/vulkan/radv_cs.h | 24 ++---
src/amd/vulkan/radv_descriptor_set.c | 18 ++--
src/amd/vulkan/radv_device.c | 66 ++++++------
src/amd/vulkan/radv_image.c | 4 +-
src/amd/vulkan/radv_meta_buffer.c | 12 +--
src/amd/vulkan/radv_private.h | 86 +++++++--------
src/amd/vulkan/radv_query.c | 12 +--
src/amd/vulkan/radv_winsys.h | 102 +++++++++---------
src/amd/vulkan/radv_wsi.c | 8 +-
src/amd/vulkan/si_cmd_buffer.c | 24 ++---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 38 +++----
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.h | 2 +-
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 116 ++++++++++-----------
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.h | 4 +-
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 4 +-
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c | 6 +-
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h | 4 +-
.../winsys/amdgpu/radv_amdgpu_winsys_public.h | 2 +-
19 files changed, 279 insertions(+), 279 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 0fb7bfa4bab..b57ce9fd1de 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -249,7 +249,7 @@ radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer
*cmd_buffer,
uint64_t min_needed)
{
uint64_t new_size;
- struct radeon_winsys_bo *bo;
+ struct radv_winsys_bo *bo;
struct radv_cmd_buffer_upload *upload;
struct radv_device *device = cmd_buffer->device;
@@ -334,7 +334,7 @@ radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer,
void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
{
struct radv_device *device = cmd_buffer->device;
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radv_winsys_cs *cs = cmd_buffer->cs;
uint64_t va;
if (!device->trace_bo)
@@ -537,7 +537,7 @@ radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
struct radv_shader_variant *shader,
struct ac_vs_output_info *outinfo)
{
- struct radeon_winsys *ws = cmd_buffer->device->ws;
+ struct radv_winsys *ws = cmd_buffer->device->ws;
uint64_t va = ws->buffer_get_va(shader->bo);
unsigned export_count;
@@ -587,7 +587,7 @@ radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
struct radv_shader_variant *shader,
struct ac_es_output_info *outinfo)
{
- struct radeon_winsys *ws = cmd_buffer->device->ws;
+ struct radv_winsys *ws = cmd_buffer->device->ws;
uint64_t va = ws->buffer_get_va(shader->bo);
ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
@@ -606,7 +606,7 @@ static void
radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
struct radv_shader_variant *shader)
{
- struct radeon_winsys *ws = cmd_buffer->device->ws;
+ struct radv_winsys *ws = cmd_buffer->device->ws;
uint64_t va = ws->buffer_get_va(shader->bo);
uint32_t rsrc2 = shader->rsrc2;
@@ -631,7 +631,7 @@ static void
radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
struct radv_shader_variant *shader)
{
- struct radeon_winsys *ws = cmd_buffer->device->ws;
+ struct radv_winsys *ws = cmd_buffer->device->ws;
uint64_t va = ws->buffer_get_va(shader->bo);
ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
@@ -734,7 +734,7 @@ static void
radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
struct radv_pipeline *pipeline)
{
- struct radeon_winsys *ws = cmd_buffer->device->ws;
+ struct radv_winsys *ws = cmd_buffer->device->ws;
struct radv_shader_variant *gs;
uint64_t va;
@@ -799,7 +799,7 @@ static void
radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
struct radv_pipeline *pipeline)
{
- struct radeon_winsys *ws = cmd_buffer->device->ws;
+ struct radv_winsys *ws = cmd_buffer->device->ws;
struct radv_shader_variant *ps;
uint64_t va;
unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
@@ -2004,7 +2004,7 @@ void radv_bind_descriptor_set(struct radv_cmd_buffer
*cmd_buffer,
struct radv_descriptor_set *set,
unsigned idx)
{
- struct radeon_winsys *ws = cmd_buffer->device->ws;
+ struct radv_winsys *ws = cmd_buffer->device->ws;
assert(!(set->layout->flags &
VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
@@ -2201,7 +2201,7 @@ VkResult radv_EndCommandBuffer(
static void
radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
{
- struct radeon_winsys *ws = cmd_buffer->device->ws;
+ struct radv_winsys *ws = cmd_buffer->device->ws;
struct radv_shader_variant *compute_shader;
struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
uint64_t va;
@@ -2703,7 +2703,7 @@ radv_emit_indirect_draw(struct radv_cmd_buffer
*cmd_buffer,
{
RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
RADV_FROM_HANDLE(radv_buffer, count_buffer, _count_buffer);
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radv_winsys_cs *cs = cmd_buffer->cs;
unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
: V_0287F0_DI_SRC_SEL_AUTO_INDEX;
uint64_t indirect_va =
cmd_buffer->device->ws->buffer_get_va(buffer->bo);
@@ -3274,7 +3274,7 @@ static void write_event(struct radv_cmd_buffer
*cmd_buffer,
VkPipelineStageFlags stageMask,
unsigned value)
{
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radv_winsys_cs *cs = cmd_buffer->cs;
uint64_t va = cmd_buffer->device->ws->buffer_get_va(event->bo);
cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
@@ -3326,7 +3326,7 @@ void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
const VkImageMemoryBarrier* pImageMemoryBarriers)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radv_winsys_cs *cs = cmd_buffer->cs;
for (unsigned i = 0; i < eventCount; ++i) {
RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h
index 0990270f5c6..fc7b2041302 100644
--- a/src/amd/vulkan/radv_cs.h
+++ b/src/amd/vulkan/radv_cs.h
@@ -30,8 +30,8 @@
#include <assert.h>
#include "r600d_common.h"
-static inline unsigned radeon_check_space(struct radeon_winsys *ws,
- struct radeon_winsys_cs *cs,
+static inline unsigned radeon_check_space(struct radv_winsys *ws,
+ struct radv_winsys_cs *cs,
unsigned needed)
{
if (cs->max_dw - cs->cdw < needed)
@@ -39,7 +39,7 @@ static inline unsigned radeon_check_space(struct
radeon_winsys *ws,
return cs->cdw + needed;
}
-static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs,
unsigned reg, unsigned num)
+static inline void radeon_set_config_reg_seq(struct radv_winsys_cs *cs,
unsigned reg, unsigned num)
{
assert(reg < R600_CONTEXT_REG_OFFSET);
assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -48,13 +48,13 @@ static inline void radeon_set_config_reg_seq(struct
radeon_winsys_cs *cs, unsign
radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
}
-static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned
reg, unsigned value)
+static inline void radeon_set_config_reg(struct radv_winsys_cs *cs, unsigned
reg, unsigned value)
{
radeon_set_config_reg_seq(cs, reg, 1);
radeon_emit(cs, value);
}
-static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs,
unsigned reg, unsigned num)
+static inline void radeon_set_context_reg_seq(struct radv_winsys_cs *cs,
unsigned reg, unsigned num)
{
assert(reg >= R600_CONTEXT_REG_OFFSET);
assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -63,14 +63,14 @@ static inline void radeon_set_context_reg_seq(struct
radeon_winsys_cs *cs, unsig
radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
}
-static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs,
unsigned reg, unsigned value)
+static inline void radeon_set_context_reg(struct radv_winsys_cs *cs, unsigned
reg, unsigned value)
{
radeon_set_context_reg_seq(cs, reg, 1);
radeon_emit(cs, value);
}
-static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
+static inline void radeon_set_context_reg_idx(struct radv_winsys_cs *cs,
unsigned reg, unsigned idx,
unsigned value)
{
@@ -81,7 +81,7 @@ static inline void radeon_set_context_reg_idx(struct
radeon_winsys_cs *cs,
radeon_emit(cs, value);
}
-static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned
reg, unsigned num)
+static inline void radeon_set_sh_reg_seq(struct radv_winsys_cs *cs, unsigned
reg, unsigned num)
{
assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -90,13 +90,13 @@ static inline void radeon_set_sh_reg_seq(struct
radeon_winsys_cs *cs, unsigned r
radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
}
-static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned
reg, unsigned value)
+static inline void radeon_set_sh_reg(struct radv_winsys_cs *cs, unsigned reg,
unsigned value)
{
radeon_set_sh_reg_seq(cs, reg, 1);
radeon_emit(cs, value);
}
-static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs,
unsigned reg, unsigned num)
+static inline void radeon_set_uconfig_reg_seq(struct radv_winsys_cs *cs,
unsigned reg, unsigned num)
{
assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
assert(cs->cdw + 2 + num <= cs->max_dw);
@@ -105,13 +105,13 @@ static inline void radeon_set_uconfig_reg_seq(struct
radeon_winsys_cs *cs, unsig
radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
}
-static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs,
unsigned reg, unsigned value)
+static inline void radeon_set_uconfig_reg(struct radv_winsys_cs *cs, unsigned
reg, unsigned value)
{
radeon_set_uconfig_reg_seq(cs, reg, 1);
radeon_emit(cs, value);
}
-static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs,
+static inline void radeon_set_uconfig_reg_idx(struct radv_winsys_cs *cs,
unsigned reg, unsigned idx,
unsigned value)
{
diff --git a/src/amd/vulkan/radv_descriptor_set.c
b/src/amd/vulkan/radv_descriptor_set.c
index ec7fd3d8cc8..3ea4936bfae 100644
--- a/src/amd/vulkan/radv_descriptor_set.c
+++ b/src/amd/vulkan/radv_descriptor_set.c
@@ -263,7 +263,7 @@ radv_descriptor_set_create(struct radv_device *device,
{
struct radv_descriptor_set *set;
unsigned range_offset = sizeof(struct radv_descriptor_set) +
- sizeof(struct radeon_winsys_bo *) * layout->buffer_count;
+ sizeof(struct radv_winsys_bo *) * layout->buffer_count;
unsigned mem_size = range_offset +
sizeof(struct radv_descriptor_range) *
layout->dynamic_offset_count;
@@ -407,7 +407,7 @@ VkResult radv_CreateDescriptorPool(
if (!(pCreateInfo->flags &
VK_DESCRIPTOR_POOL_CREATE_FREE_DESCRIPTOR_SET_BIT)) {
uint64_t host_size = pCreateInfo->maxSets * sizeof(struct
radv_descriptor_set);
- host_size += sizeof(struct radeon_winsys_bo*) * bo_count;
+ host_size += sizeof(struct radv_winsys_bo*) * bo_count;
host_size += sizeof(struct radv_descriptor_range) * range_count;
size += host_size;
}
@@ -536,7 +536,7 @@ VkResult radv_FreeDescriptorSets(
static void write_texel_buffer_descriptor(struct radv_device *device,
struct radv_cmd_buffer *cmd_buffer,
unsigned *dst,
- struct radeon_winsys_bo **buffer_list,
+ struct radv_winsys_bo **buffer_list,
const VkBufferView _buffer_view)
{
RADV_FROM_HANDLE(radv_buffer_view, buffer_view, _buffer_view);
@@ -552,7 +552,7 @@ static void write_texel_buffer_descriptor(struct
radv_device *device,
static void write_buffer_descriptor(struct radv_device *device,
struct radv_cmd_buffer *cmd_buffer,
unsigned *dst,
- struct radeon_winsys_bo **buffer_list,
+ struct radv_winsys_bo **buffer_list,
const VkDescriptorBufferInfo *buffer_info)
{
RADV_FROM_HANDLE(radv_buffer, buffer, buffer_info->buffer);
@@ -581,7 +581,7 @@ static void write_buffer_descriptor(struct radv_device
*device,
static void write_dynamic_buffer_descriptor(struct radv_device *device,
struct radv_descriptor_range
*range,
- struct radeon_winsys_bo
**buffer_list,
+ struct radv_winsys_bo
**buffer_list,
const VkDescriptorBufferInfo
*buffer_info)
{
RADV_FROM_HANDLE(radv_buffer, buffer, buffer_info->buffer);
@@ -602,7 +602,7 @@ static void
write_image_descriptor(struct radv_device *device,
struct radv_cmd_buffer *cmd_buffer,
unsigned *dst,
- struct radeon_winsys_bo **buffer_list,
+ struct radv_winsys_bo **buffer_list,
const VkDescriptorImageInfo *image_info)
{
RADV_FROM_HANDLE(radv_image_view, iview, image_info->imageView);
@@ -619,7 +619,7 @@ static void
write_combined_image_sampler_descriptor(struct radv_device *device,
struct radv_cmd_buffer *cmd_buffer,
unsigned *dst,
- struct radeon_winsys_bo **buffer_list,
+ struct radv_winsys_bo **buffer_list,
const VkDescriptorImageInfo *image_info,
bool has_sampler)
{
@@ -658,7 +658,7 @@ void radv_update_descriptor_sets(
const struct radv_descriptor_set_binding_layout *binding_layout
=
set->layout->binding + writeset->dstBinding;
uint32_t *ptr = set->mapped_ptr;
- struct radeon_winsys_bo **buffer_list = set->descriptors;
+ struct radv_winsys_bo **buffer_list = set->descriptors;
/* Immutable samplers are not copied into push descriptors when
they are
* allocated, so if we are writing push descriptors we have to
copy the
* immutable samplers into them now.
@@ -837,7 +837,7 @@ void radv_update_descriptor_set_with_template(struct
radv_device *device,
uint32_t i;
for (i = 0; i < templ->entry_count; ++i) {
- struct radeon_winsys_bo **buffer_list = set->descriptors +
templ->entry[i].buffer_offset;
+ struct radv_winsys_bo **buffer_list = set->descriptors +
templ->entry[i].buffer_offset;
uint32_t *pDst = set->mapped_ptr + templ->entry[i].dst_offset;
const uint8_t *pSrc = ((const uint8_t *) pData) +
templ->entry[i].src_offset;
uint32_t j;
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 1ea69608a14..52de47f4bdc 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1288,7 +1288,7 @@ void radv_GetDeviceQueue(
}
static void radv_dump_trace(struct radv_device *device,
- struct radeon_winsys_cs *cs)
+ struct radv_winsys_cs *cs)
{
const char *filename = getenv("RADV_TRACE_FILE");
FILE *f = fopen(filename, "w");
@@ -1307,13 +1307,13 @@ fill_geom_tess_rings(struct radv_queue *queue,
uint32_t *map,
bool add_sample_positions,
uint32_t esgs_ring_size,
- struct radeon_winsys_bo *esgs_ring_bo,
+ struct radv_winsys_bo *esgs_ring_bo,
uint32_t gsvs_ring_size,
- struct radeon_winsys_bo *gsvs_ring_bo,
+ struct radv_winsys_bo *gsvs_ring_bo,
uint32_t tess_factor_ring_size,
- struct radeon_winsys_bo *tess_factor_ring_bo,
+ struct radv_winsys_bo *tess_factor_ring_bo,
uint32_t tess_offchip_ring_size,
- struct radeon_winsys_bo *tess_offchip_ring_bo)
+ struct radv_winsys_bo *tess_offchip_ring_bo)
{
uint64_t esgs_va = 0, gsvs_va = 0;
uint64_t tess_factor_va = 0, tess_offchip_va = 0;
@@ -1504,17 +1504,17 @@ radv_get_preamble_cs(struct radv_queue *queue,
uint32_t gsvs_ring_size,
bool needs_tess_rings,
bool needs_sample_positions,
- struct radeon_winsys_cs **initial_preamble_cs,
- struct radeon_winsys_cs **continue_preamble_cs)
-{
- struct radeon_winsys_bo *scratch_bo = NULL;
- struct radeon_winsys_bo *descriptor_bo = NULL;
- struct radeon_winsys_bo *compute_scratch_bo = NULL;
- struct radeon_winsys_bo *esgs_ring_bo = NULL;
- struct radeon_winsys_bo *gsvs_ring_bo = NULL;
- struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
- struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
- struct radeon_winsys_cs *dest_cs[2] = {0};
+ struct radv_winsys_cs **initial_preamble_cs,
+ struct radv_winsys_cs **continue_preamble_cs)
+{
+ struct radv_winsys_bo *scratch_bo = NULL;
+ struct radv_winsys_bo *descriptor_bo = NULL;
+ struct radv_winsys_bo *compute_scratch_bo = NULL;
+ struct radv_winsys_bo *esgs_ring_bo = NULL;
+ struct radv_winsys_bo *gsvs_ring_bo = NULL;
+ struct radv_winsys_bo *tess_factor_ring_bo = NULL;
+ struct radv_winsys_bo *tess_offchip_ring_bo = NULL;
+ struct radv_winsys_cs *dest_cs[2] = {0};
bool add_tess_rings = false, add_sample_positions = false;
unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
unsigned max_offchip_buffers;
@@ -1641,7 +1641,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
descriptor_bo = queue->descriptor_bo;
for(int i = 0; i < 2; ++i) {
- struct radeon_winsys_cs *cs = NULL;
+ struct radv_winsys_cs *cs = NULL;
cs = queue->device->ws->cs_create(queue->device->ws,
queue->queue_family_index ?
RING_COMPUTE : RING_GFX);
if (!cs)
@@ -1865,14 +1865,14 @@ VkResult radv_QueueSubmit(
{
RADV_FROM_HANDLE(radv_queue, queue, _queue);
RADV_FROM_HANDLE(radv_fence, fence, _fence);
- struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
- struct radeon_winsys_ctx *ctx = queue->hw_ctx;
+ struct radv_winsys_fence *base_fence = fence ? fence->fence : NULL;
+ struct radv_winsys_ctx *ctx = queue->hw_ctx;
int ret;
uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
uint32_t scratch_size = 0;
uint32_t compute_scratch_size = 0;
uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
- struct radeon_winsys_cs *initial_preamble_cs = NULL,
*continue_preamble_cs = NULL;
+ struct radv_winsys_cs *initial_preamble_cs = NULL,
*continue_preamble_cs = NULL;
VkResult result;
bool fence_emitted = false;
bool tess_rings_needed = false;
@@ -1903,7 +1903,7 @@ VkResult radv_QueueSubmit(
return result;
for (uint32_t i = 0; i < submitCount; i++) {
- struct radeon_winsys_cs **cs_array;
+ struct radv_winsys_cs **cs_array;
bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
bool can_patch = !do_flush;
uint32_t advance;
@@ -1913,9 +1913,9 @@ VkResult radv_QueueSubmit(
ret = queue->device->ws->cs_submit(ctx,
queue->queue_idx,
&queue->device->empty_cs[queue->queue_family_index],
1, NULL,
NULL,
- (struct
radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
+ (struct
radv_winsys_sem **)pSubmits[i].pWaitSemaphores,
pSubmits[i].waitSemaphoreCount,
- (struct
radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
+ (struct
radv_winsys_sem **)pSubmits[i].pSignalSemaphores,
pSubmits[i].signalSemaphoreCount,
false,
base_fence);
if (ret) {
@@ -1927,7 +1927,7 @@ VkResult radv_QueueSubmit(
continue;
}
- cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
+ cs_array = malloc(sizeof(struct radv_winsys_cs *) *
(pSubmits[i].commandBufferCount
+ do_flush));
if(do_flush)
@@ -1956,9 +1956,9 @@ VkResult radv_QueueSubmit(
ret = queue->device->ws->cs_submit(ctx,
queue->queue_idx, cs_array + j,
advance,
initial_preamble_cs, continue_preamble_cs,
- (struct
radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
+ (struct radv_winsys_sem
**)pSubmits[i].pWaitSemaphores,
b ?
pSubmits[i].waitSemaphoreCount : 0,
- (struct
radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
+ (struct radv_winsys_sem
**)pSubmits[i].pSignalSemaphores,
e ?
pSubmits[i].signalSemaphoreCount : 0,
can_patch, base_fence);
@@ -2054,7 +2054,7 @@ bool radv_get_memory_fd(struct radv_device *device,
struct radv_device_memory *memory,
int *pFD)
{
- struct radeon_bo_metadata metadata;
+ struct radv_bo_metadata metadata;
if (memory->image) {
radv_init_metadata(device, memory->image, &metadata);
@@ -2355,7 +2355,7 @@ radv_sparse_image_opaque_bind_memory(struct radv_device
*device,
{
RADV_FROM_HANDLE(radv_fence, fence, _fence);
RADV_FROM_HANDLE(radv_queue, queue, _queue);
- struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
+ struct radv_winsys_fence *base_fence = fence ? fence->fence : NULL;
bool fence_emitted = false;
for (uint32_t i = 0; i < bindInfoCount; ++i) {
@@ -2373,9 +2373,9 @@ radv_sparse_image_opaque_bind_memory(struct radv_device
*device,
queue->device->ws->cs_submit(queue->hw_ctx,
queue->queue_idx,
&queue->device->empty_cs[queue->queue_family_index],
1, NULL, NULL,
- (struct radeon_winsys_sem
**)pBindInfo[i].pWaitSemaphores,
+ (struct radv_winsys_sem
**)pBindInfo[i].pWaitSemaphores,
pBindInfo[i].waitSemaphoreCount,
- (struct radeon_winsys_sem
**)pBindInfo[i].pSignalSemaphores,
+ (struct radv_winsys_sem
**)pBindInfo[i].pSignalSemaphores,
pBindInfo[i].signalSemaphoreCount,
false, base_fence);
fence_emitted = true;
@@ -2518,13 +2518,13 @@ VkResult radv_CreateSemaphore(
VkSemaphore* pSemaphore)
{
RADV_FROM_HANDLE(radv_device, device, _device);
- struct radeon_winsys_sem *sem;
+ struct radv_winsys_sem *sem;
sem = device->ws->create_sem(device->ws);
if (!sem)
return VK_ERROR_OUT_OF_HOST_MEMORY;
- *pSemaphore = radeon_winsys_sem_to_handle(sem);
+ *pSemaphore = radv_winsys_sem_to_handle(sem);
return VK_SUCCESS;
}
@@ -2534,7 +2534,7 @@ void radv_DestroySemaphore(
const VkAllocationCallbacks* pAllocator)
{
RADV_FROM_HANDLE(radv_device, device, _device);
- RADV_FROM_HANDLE(radeon_winsys_sem, sem, _semaphore);
+ RADV_FROM_HANDLE(radv_winsys_sem, sem, _semaphore);
if (!_semaphore)
return;
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 37610f1c249..d434bec6738 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -506,7 +506,7 @@ si_make_texture_descriptor(struct radv_device *device,
static void
radv_query_opaque_metadata(struct radv_device *device,
struct radv_image *image,
- struct radeon_bo_metadata *md)
+ struct radv_bo_metadata *md)
{
static const VkComponentMapping fixedmapping;
uint32_t desc[8], i;
@@ -555,7 +555,7 @@ radv_query_opaque_metadata(struct radv_device *device,
void
radv_init_metadata(struct radv_device *device,
struct radv_image *image,
- struct radeon_bo_metadata *metadata)
+ struct radv_bo_metadata *metadata)
{
struct radeon_surf *surface = &image->surface;
diff --git a/src/amd/vulkan/radv_meta_buffer.c
b/src/amd/vulkan/radv_meta_buffer.c
index a8a41e05fa3..dab9b745bc3 100644
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -295,7 +295,7 @@ void radv_device_finish_meta_buffer_state(struct
radv_device *device)
}
static void fill_buffer_shader(struct radv_cmd_buffer *cmd_buffer,
- struct radeon_winsys_bo *bo,
+ struct radv_winsys_bo *bo,
uint64_t offset, uint64_t size, uint32_t value)
{
struct radv_device *device = cmd_buffer->device;
@@ -344,8 +344,8 @@ static void fill_buffer_shader(struct radv_cmd_buffer
*cmd_buffer,
}
static void copy_buffer_shader(struct radv_cmd_buffer *cmd_buffer,
- struct radeon_winsys_bo *src_bo,
- struct radeon_winsys_bo *dst_bo,
+ struct radv_winsys_bo *src_bo,
+ struct radv_winsys_bo *dst_bo,
uint64_t src_offset, uint64_t dst_offset,
uint64_t size)
{
@@ -409,7 +409,7 @@ static void copy_buffer_shader(struct radv_cmd_buffer
*cmd_buffer,
void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
- struct radeon_winsys_bo *bo,
+ struct radv_winsys_bo *bo,
uint64_t offset, uint64_t size, uint32_t value)
{
assert(!(offset & 3));
@@ -427,8 +427,8 @@ void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
static
void radv_copy_buffer(struct radv_cmd_buffer *cmd_buffer,
- struct radeon_winsys_bo *src_bo,
- struct radeon_winsys_bo *dst_bo,
+ struct radv_winsys_bo *src_bo,
+ struct radv_winsys_bo *dst_bo,
uint64_t src_offset, uint64_t dst_offset,
uint64_t size)
{
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index d13e4190510..6640e7f8639 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -263,7 +263,7 @@ struct radv_physical_device {
struct radv_instance * instance;
- struct radeon_winsys *ws;
+ struct radv_winsys *ws;
struct radeon_info rad_info;
char path[20];
const char * name;
@@ -481,7 +481,7 @@ enum ring_type radv_queue_family_to_ring(int f);
struct radv_queue {
VK_LOADER_DATA _loader_data;
struct radv_device * device;
- struct radeon_winsys_ctx *hw_ctx;
+ struct radv_winsys_ctx *hw_ctx;
int queue_family_index;
int queue_idx;
@@ -492,15 +492,15 @@ struct radv_queue {
bool has_tess_rings;
bool has_sample_positions;
- struct radeon_winsys_bo *scratch_bo;
- struct radeon_winsys_bo *descriptor_bo;
- struct radeon_winsys_bo *compute_scratch_bo;
- struct radeon_winsys_bo *esgs_ring_bo;
- struct radeon_winsys_bo *gsvs_ring_bo;
- struct radeon_winsys_bo *tess_factor_ring_bo;
- struct radeon_winsys_bo *tess_offchip_ring_bo;
- struct radeon_winsys_cs *initial_preamble_cs;
- struct radeon_winsys_cs *continue_preamble_cs;
+ struct radv_winsys_bo *scratch_bo;
+ struct radv_winsys_bo *descriptor_bo;
+ struct radv_winsys_bo *compute_scratch_bo;
+ struct radv_winsys_bo *esgs_ring_bo;
+ struct radv_winsys_bo *gsvs_ring_bo;
+ struct radv_winsys_bo *tess_factor_ring_bo;
+ struct radv_winsys_bo *tess_offchip_ring_bo;
+ struct radv_winsys_cs *initial_preamble_cs;
+ struct radv_winsys_cs *continue_preamble_cs;
};
struct radv_device {
@@ -509,15 +509,15 @@ struct radv_device {
VkAllocationCallbacks alloc;
struct radv_instance * instance;
- struct radeon_winsys *ws;
+ struct radv_winsys *ws;
struct radv_meta_state meta_state;
struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
int queue_count[RADV_MAX_QUEUE_FAMILIES];
- struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
- struct radeon_winsys_cs *flush_cs[RADV_MAX_QUEUE_FAMILIES];
- struct radeon_winsys_cs *flush_shader_cs[RADV_MAX_QUEUE_FAMILIES];
+ struct radv_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
+ struct radv_winsys_cs *flush_cs[RADV_MAX_QUEUE_FAMILIES];
+ struct radv_winsys_cs *flush_shader_cs[RADV_MAX_QUEUE_FAMILIES];
uint64_t debug_flags;
bool llvm_supports_spill;
@@ -538,9 +538,9 @@ struct radv_device {
/* CIK and later */
uint32_t gfx_init_size_dw;
- struct radeon_winsys_bo *gfx_init;
+ struct radv_winsys_bo *gfx_init;
- struct radeon_winsys_bo *trace_bo;
+ struct radv_winsys_bo *trace_bo;
uint32_t *trace_id_ptr;
struct radv_physical_device *physical_device;
@@ -550,7 +550,7 @@ struct radv_device {
};
struct radv_device_memory {
- struct radeon_winsys_bo *bo;
+ struct radv_winsys_bo *bo;
/* for dedicated allocations */
struct radv_image *image;
struct radv_buffer *buffer;
@@ -569,14 +569,14 @@ struct radv_descriptor_set {
const struct radv_descriptor_set_layout *layout;
uint32_t size;
- struct radeon_winsys_bo *bo;
+ struct radv_winsys_bo *bo;
uint64_t va;
uint32_t *mapped_ptr;
struct radv_descriptor_range *dynamic_descriptors;
struct list_head vram_list;
- struct radeon_winsys_bo *descriptors[0];
+ struct radv_winsys_bo *descriptors[0];
};
struct radv_push_descriptor_set
@@ -586,7 +586,7 @@ struct radv_push_descriptor_set
};
struct radv_descriptor_pool {
- struct radeon_winsys_bo *bo;
+ struct radv_winsys_bo *bo;
uint8_t *mapped_ptr;
uint64_t current_offset;
uint64_t size;
@@ -636,7 +636,7 @@ struct radv_buffer {
VkBufferCreateFlags flags;
/* Set when bound */
- struct radeon_winsys_bo * bo;
+ struct radv_winsys_bo * bo;
VkDeviceSize offset;
};
@@ -789,7 +789,7 @@ struct radv_cmd_buffer_upload {
uint8_t *map;
unsigned offset;
uint64_t size;
- struct radeon_winsys_bo *upload_bo;
+ struct radv_winsys_bo *upload_bo;
struct list_head list;
};
@@ -803,7 +803,7 @@ struct radv_cmd_buffer {
VkCommandBufferUsageFlags usage_flags;
VkCommandBufferLevel level;
- struct radeon_winsys_cs *cs;
+ struct radv_winsys_cs *cs;
struct radv_cmd_state state;
uint32_t queue_family_index;
@@ -826,7 +826,7 @@ struct radv_cmd_buffer {
int ring_offsets_idx; /* just used for verification */
uint32_t gfx9_fence_offset;
- struct radeon_winsys_bo *gfx9_fence_bo;
+ struct radv_winsys_bo *gfx9_fence_bo;
uint32_t gfx9_fence_idx;
};
@@ -839,15 +839,15 @@ void si_init_config(struct radv_cmd_buffer *cmd_buffer);
void cik_create_gfx_config(struct radv_device *device);
-void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
+void si_write_viewport(struct radv_winsys_cs *cs, int first_vp,
int count, const VkViewport *viewports);
-void si_write_scissors(struct radeon_winsys_cs *cs, int first,
+void si_write_scissors(struct radv_winsys_cs *cs, int first,
int count, const VkRect2D *scissors,
const VkViewport *viewports, bool can_use_guardband);
uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
bool instanced_draw, bool indirect_draw,
uint32_t draw_vertex_count);
-void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
+void si_cs_emit_write_event_eop(struct radv_winsys_cs *cs,
enum chip_class chip_class,
bool is_mec,
unsigned event, unsigned event_flags,
@@ -856,10 +856,10 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs
*cs,
uint32_t old_fence,
uint32_t new_fence);
-void si_emit_wait_fence(struct radeon_winsys_cs *cs,
+void si_emit_wait_fence(struct radv_winsys_cs *cs,
uint64_t va, uint32_t ref,
uint32_t mask);
-void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
+void si_cs_emit_cache_flush(struct radv_winsys_cs *cs,
enum chip_class chip_class,
uint32_t *fence_ptr, uint64_t va,
bool is_mec,
@@ -896,7 +896,7 @@ void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer);
void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
-void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int
nr_samples);
+void radv_cayman_emit_msaa_sample_locs(struct radv_winsys_cs *cs, int
nr_samples);
unsigned radv_cayman_get_maxdist(int log_samples);
void radv_device_init_msaa(struct radv_device *device);
void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
@@ -908,7 +908,7 @@ void radv_set_color_clear_regs(struct radv_cmd_buffer
*cmd_buffer,
int idx,
uint32_t color_values[2]);
void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
- struct radeon_winsys_bo *bo,
+ struct radv_winsys_bo *bo,
uint64_t offset, uint64_t size, uint32_t value);
void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
bool radv_get_memory_fd(struct radv_device *device,
@@ -927,7 +927,7 @@ void radv_unaligned_dispatch(
uint32_t z);
struct radv_event {
- struct radeon_winsys_bo *bo;
+ struct radv_winsys_bo *bo;
uint64_t *map;
};
@@ -974,7 +974,7 @@ mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
struct radv_shader_variant {
uint32_t ref_count;
- struct radeon_winsys_bo *bo;
+ struct radv_winsys_bo *bo;
struct ac_shader_config config;
struct ac_shader_variant_info info;
unsigned rsrc1;
@@ -1200,7 +1200,7 @@ struct radv_image {
unsigned queue_family_mask;
/* Set when bound */
- struct radeon_winsys_bo *bo;
+ struct radv_winsys_bo *bo;
VkDeviceSize offset;
uint32_t dcc_offset;
uint32_t htile_offset;
@@ -1250,15 +1250,15 @@ radv_get_levelCount(const struct radv_image *image,
image->info.levels - range->baseMipLevel : range->levelCount;
}
-struct radeon_bo_metadata;
+struct radv_bo_metadata;
void
radv_init_metadata(struct radv_device *device,
struct radv_image *image,
- struct radeon_bo_metadata *metadata);
+ struct radv_bo_metadata *metadata);
struct radv_image_view {
struct radv_image *image; /**< VkImageViewCreateInfo::image */
- struct radeon_winsys_bo *bo;
+ struct radv_winsys_bo *bo;
VkImageViewType type;
VkImageAspectFlags aspect_mask;
@@ -1289,7 +1289,7 @@ void radv_image_view_init(struct radv_image_view *view,
VkImageUsageFlags usage_mask);
struct radv_buffer_view {
- struct radeon_winsys_bo *bo;
+ struct radv_winsys_bo *bo;
VkFormat vk_format;
uint64_t range; /**< VkBufferViewCreateInfo::range */
uint32_t state[4];
@@ -1444,7 +1444,7 @@ VkResult radv_device_init_meta(struct radv_device
*device);
void radv_device_finish_meta(struct radv_device *device);
struct radv_query_pool {
- struct radeon_winsys_bo *bo;
+ struct radv_winsys_bo *bo;
uint32_t stride;
uint32_t availability_offset;
char *ptr;
@@ -1481,12 +1481,12 @@ void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer,
struct radv_image *image, uint32_t value);
struct radv_fence {
- struct radeon_winsys_fence *fence;
+ struct radv_winsys_fence *fence;
bool submitted;
bool signalled;
};
-struct radeon_winsys_sem;
+struct radv_winsys_sem;
#define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
\
@@ -1545,6 +1545,6 @@ RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool,
VkQueryPool)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
-RADV_DEFINE_NONDISP_HANDLE_CASTS(radeon_winsys_sem, VkSemaphore)
+RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_winsys_sem, VkSemaphore)
#endif /* RADV_PRIVATE_H */
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 03b5af16a55..4e21efa611a 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -643,8 +643,8 @@ void radv_device_finish_meta_query_state(struct radv_device
*device)
static void radv_query_shader(struct radv_cmd_buffer *cmd_buffer,
VkPipeline pipeline,
- struct radeon_winsys_bo *src_bo,
- struct radeon_winsys_bo *dst_bo,
+ struct radv_winsys_bo *src_bo,
+ struct radv_winsys_bo *dst_bo,
uint64_t src_offset, uint64_t dst_offset,
uint32_t src_stride, uint32_t dst_stride,
uint32_t count, uint32_t flags,
@@ -950,7 +950,7 @@ void radv_CmdCopyQueryPoolResults(
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
RADV_FROM_HANDLE(radv_buffer, dst_buffer, dstBuffer);
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radv_winsys_cs *cs = cmd_buffer->cs;
unsigned elem_size = (flags & VK_QUERY_RESULT_64_BIT) ? 8 : 4;
uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
uint64_t dest_va =
cmd_buffer->device->ws->buffer_get_va(dst_buffer->bo);
@@ -1077,7 +1077,7 @@ void radv_CmdBeginQuery(
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radv_winsys_cs *cs = cmd_buffer->cs;
uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
va += pool->stride * query;
@@ -1117,7 +1117,7 @@ void radv_CmdEndQuery(
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radv_winsys_cs *cs = cmd_buffer->cs;
uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
uint64_t avail_va = va + pool->availability_offset + 4 * query;
va += pool->stride * query;
@@ -1168,7 +1168,7 @@ void radv_CmdWriteTimestamp(
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
bool mec = radv_cmd_buffer_uses_mec(cmd_buffer);
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radv_winsys_cs *cs = cmd_buffer->cs;
uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo);
uint64_t avail_va = va + pool->availability_offset + 4 * query;
uint64_t query_va = va + pool->stride * query;
diff --git a/src/amd/vulkan/radv_winsys.h b/src/amd/vulkan/radv_winsys.h
index b4a4793a127..f904cd653d4 100644
--- a/src/amd/vulkan/radv_winsys.h
+++ b/src/amd/vulkan/radv_winsys.h
@@ -2,7 +2,7 @@
* Copyright © 2016 Red Hat.
* Copyright © 2016 Bas Nieuwenhuizen
*
- * Based on radeon_winsys.h which is:
+ * Based on radv_winsys.h which is:
* Copyright 2008 Corbin Simpson <mostawesomed...@gmail.com>
* Copyright 2010 Marek Olšák <mar...@gmail.com>
*
@@ -69,7 +69,7 @@ enum ring_type {
RING_LAST,
};
-struct radeon_winsys_cs {
+struct radv_winsys_cs {
unsigned cdw; /* Number of used dwords. */
unsigned max_dw; /* Maximum number of dwords. */
uint32_t *buf; /* The base pointer of the chunk. */
@@ -99,7 +99,7 @@ enum radeon_bo_layout {
};
/* Tiling info for display code, DRI sharing, and other data. */
-struct radeon_bo_metadata {
+struct radv_bo_metadata {
/* Tiling flags describing the texture layout for display code
* and DRI sharing.
*/
@@ -131,107 +131,107 @@ struct radeon_bo_metadata {
uint32_t metadata[64];
};
-struct radeon_winsys_bo;
-struct radeon_winsys_fence;
-struct radeon_winsys_sem;
+struct radv_winsys_bo;
+struct radv_winsys_fence;
+struct radv_winsys_sem;
-struct radeon_winsys {
- void (*destroy)(struct radeon_winsys *ws);
+struct radv_winsys {
+ void (*destroy)(struct radv_winsys *ws);
- void (*query_info)(struct radeon_winsys *ws,
+ void (*query_info)(struct radv_winsys *ws,
struct radeon_info *info);
- struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws,
+ struct radv_winsys_bo *(*buffer_create)(struct radv_winsys *ws,
uint64_t size,
unsigned alignment,
enum radeon_bo_domain domain,
enum radeon_bo_flag flags);
- void (*buffer_destroy)(struct radeon_winsys_bo *bo);
- void *(*buffer_map)(struct radeon_winsys_bo *bo);
+ void (*buffer_destroy)(struct radv_winsys_bo *bo);
+ void *(*buffer_map)(struct radv_winsys_bo *bo);
- struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws,
+ struct radv_winsys_bo *(*buffer_from_fd)(struct radv_winsys *ws,
int fd,
unsigned *stride, unsigned
*offset);
- bool (*buffer_get_fd)(struct radeon_winsys *ws,
- struct radeon_winsys_bo *bo,
+ bool (*buffer_get_fd)(struct radv_winsys *ws,
+ struct radv_winsys_bo *bo,
int *fd);
- void (*buffer_unmap)(struct radeon_winsys_bo *bo);
+ void (*buffer_unmap)(struct radv_winsys_bo *bo);
- uint64_t (*buffer_get_va)(struct radeon_winsys_bo *bo);
+ uint64_t (*buffer_get_va)(struct radv_winsys_bo *bo);
- void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
- struct radeon_bo_metadata *md);
+ void (*buffer_set_metadata)(struct radv_winsys_bo *bo,
+ struct radv_bo_metadata *md);
- void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
+ void (*buffer_virtual_bind)(struct radv_winsys_bo *parent,
uint64_t offset, uint64_t size,
- struct radeon_winsys_bo *bo, uint64_t
bo_offset);
- struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws);
- void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
+ struct radv_winsys_bo *bo, uint64_t
bo_offset);
+ struct radv_winsys_ctx *(*ctx_create)(struct radv_winsys *ws);
+ void (*ctx_destroy)(struct radv_winsys_ctx *ctx);
- bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx,
+ bool (*ctx_wait_idle)(struct radv_winsys_ctx *ctx,
enum ring_type ring_type, int ring_index);
- struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws,
+ struct radv_winsys_cs *(*cs_create)(struct radv_winsys *ws,
enum ring_type ring_type);
- void (*cs_destroy)(struct radeon_winsys_cs *cs);
+ void (*cs_destroy)(struct radv_winsys_cs *cs);
- void (*cs_reset)(struct radeon_winsys_cs *cs);
+ void (*cs_reset)(struct radv_winsys_cs *cs);
- bool (*cs_finalize)(struct radeon_winsys_cs *cs);
+ bool (*cs_finalize)(struct radv_winsys_cs *cs);
- void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size);
+ void (*cs_grow)(struct radv_winsys_cs * cs, size_t min_size);
- int (*cs_submit)(struct radeon_winsys_ctx *ctx,
+ int (*cs_submit)(struct radv_winsys_ctx *ctx,
int queue_index,
- struct radeon_winsys_cs **cs_array,
+ struct radv_winsys_cs **cs_array,
unsigned cs_count,
- struct radeon_winsys_cs *initial_preamble_cs,
- struct radeon_winsys_cs *continue_preamble_cs,
- struct radeon_winsys_sem **wait_sem,
+ struct radv_winsys_cs *initial_preamble_cs,
+ struct radv_winsys_cs *continue_preamble_cs,
+ struct radv_winsys_sem **wait_sem,
unsigned wait_sem_count,
- struct radeon_winsys_sem **signal_sem,
+ struct radv_winsys_sem **signal_sem,
unsigned signal_sem_count,
bool can_patch,
- struct radeon_winsys_fence *fence);
+ struct radv_winsys_fence *fence);
- void (*cs_add_buffer)(struct radeon_winsys_cs *cs,
- struct radeon_winsys_bo *bo,
+ void (*cs_add_buffer)(struct radv_winsys_cs *cs,
+ struct radv_winsys_bo *bo,
uint8_t priority);
- void (*cs_execute_secondary)(struct radeon_winsys_cs *parent,
- struct radeon_winsys_cs *child);
+ void (*cs_execute_secondary)(struct radv_winsys_cs *parent,
+ struct radv_winsys_cs *child);
- void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, uint32_t
trace_id);
+ void (*cs_dump)(struct radv_winsys_cs *cs, FILE* file, uint32_t
trace_id);
- int (*surface_init)(struct radeon_winsys *ws,
+ int (*surface_init)(struct radv_winsys *ws,
const struct ac_surf_info *surf_info,
struct radeon_surf *surf);
- int (*surface_best)(struct radeon_winsys *ws,
+ int (*surface_best)(struct radv_winsys *ws,
struct radeon_surf *surf);
- struct radeon_winsys_fence *(*create_fence)();
- void (*destroy_fence)(struct radeon_winsys_fence *fence);
- bool (*fence_wait)(struct radeon_winsys *ws,
- struct radeon_winsys_fence *fence,
+ struct radv_winsys_fence *(*create_fence)();
+ void (*destroy_fence)(struct radv_winsys_fence *fence);
+ bool (*fence_wait)(struct radv_winsys *ws,
+ struct radv_winsys_fence *fence,
bool absolute,
uint64_t timeout);
- struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws);
- void (*destroy_sem)(struct radeon_winsys_sem *sem);
+ struct radv_winsys_sem *(*create_sem)(struct radv_winsys *ws);
+ void (*destroy_sem)(struct radv_winsys_sem *sem);
};
-static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value)
+static inline void radeon_emit(struct radv_winsys_cs *cs, uint32_t value)
{
cs->buf[cs->cdw++] = value;
}
-static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
+static inline void radeon_emit_array(struct radv_winsys_cs *cs,
const uint32_t *values, unsigned count)
{
memcpy(cs->buf + cs->cdw, values, count * 4);
diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index cdb04ca9628..7ffab3a2621 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -458,7 +458,7 @@ VkResult radv_QueuePresentKHR(
for (uint32_t i = 0; i < pPresentInfo->swapchainCount; i++) {
RADV_FROM_HANDLE(wsi_swapchain, swapchain,
pPresentInfo->pSwapchains[i]);
- struct radeon_winsys_cs *cs;
+ struct radv_winsys_cs *cs;
const VkPresentRegionKHR *region = NULL;
VkResult item_result;
@@ -485,12 +485,12 @@ VkResult radv_QueuePresentKHR(
} else
cs = queue->device->empty_cs[queue->queue_family_index];
RADV_FROM_HANDLE(radv_fence, fence, swapchain->fences[0]);
- struct radeon_winsys_fence *base_fence = fence->fence;
- struct radeon_winsys_ctx *ctx = queue->hw_ctx;
+ struct radv_winsys_fence *base_fence = fence->fence;
+ struct radv_winsys_ctx *ctx = queue->hw_ctx;
queue->device->ws->cs_submit(ctx, queue->queue_idx,
&cs,
1, NULL, NULL,
- (struct radeon_winsys_sem
**)pPresentInfo->pWaitSemaphores,
+ (struct radv_winsys_sem
**)pPresentInfo->pWaitSemaphores,
pPresentInfo->waitSemaphoreCount,
NULL, 0, false, base_fence);
fence->submitted = true;
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 33414c1cbcd..25d3b6450be 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -38,7 +38,7 @@
static void
si_write_harvested_raster_configs(struct radv_physical_device *physical_device,
- struct radeon_winsys_cs *cs,
+ struct radv_winsys_cs *cs,
unsigned raster_config,
unsigned raster_config_1)
{
@@ -173,7 +173,7 @@ si_write_harvested_raster_configs(struct
radv_physical_device *physical_device,
static void
si_emit_compute(struct radv_physical_device *physical_device,
- struct radeon_winsys_cs *cs)
+ struct radv_winsys_cs *cs)
{
radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
radeon_emit(cs, 0);
@@ -219,7 +219,7 @@ si_init_compute(struct radv_cmd_buffer *cmd_buffer)
static void
si_emit_config(struct radv_physical_device *physical_device,
- struct radeon_winsys_cs *cs)
+ struct radv_winsys_cs *cs)
{
unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends,
16);
unsigned rb_mask = physical_device->rad_info.enabled_rb_mask;
@@ -500,7 +500,7 @@ void si_init_config(struct radv_cmd_buffer *cmd_buffer)
void
cik_create_gfx_config(struct radv_device *device)
{
- struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws,
RING_GFX);
+ struct radv_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX);
if (!cs)
return;
@@ -555,7 +555,7 @@ get_viewport_xform(const VkViewport *viewport,
}
void
-si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
+si_write_viewport(struct radv_winsys_cs *cs, int first_vp,
int count, const VkViewport *viewports)
{
int i;
@@ -614,7 +614,7 @@ static VkRect2D si_intersect_scissor(const VkRect2D *a,
const VkRect2D *b) {
}
void
-si_write_scissors(struct radeon_winsys_cs *cs, int first,
+si_write_scissors(struct radv_winsys_cs *cs, int first,
int count, const VkRect2D *scissors,
const VkViewport *viewports, bool can_use_guardband)
{
@@ -815,7 +815,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer,
}
-void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
+void si_cs_emit_write_event_eop(struct radv_winsys_cs *cs,
enum chip_class chip_class,
bool is_mec,
unsigned event, unsigned event_flags,
@@ -864,7 +864,7 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
}
void
-si_emit_wait_fence(struct radeon_winsys_cs *cs,
+si_emit_wait_fence(struct radv_winsys_cs *cs,
uint64_t va, uint32_t ref,
uint32_t mask)
{
@@ -878,7 +878,7 @@ si_emit_wait_fence(struct radeon_winsys_cs *cs,
}
static void
-si_emit_acquire_mem(struct radeon_winsys_cs *cs,
+si_emit_acquire_mem(struct radv_winsys_cs *cs,
bool is_mec, bool is_gfx9,
unsigned cp_coher_cntl)
{
@@ -903,7 +903,7 @@ si_emit_acquire_mem(struct radeon_winsys_cs *cs,
}
void
-si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
+si_cs_emit_cache_flush(struct radv_winsys_cs *cs,
enum chip_class chip_class,
uint32_t *flush_cnt,
uint64_t flush_va,
@@ -1146,7 +1146,7 @@ static void si_emit_cp_dma(struct radv_cmd_buffer
*cmd_buffer,
uint64_t dst_va, uint64_t src_va,
unsigned size, unsigned flags)
{
- struct radeon_winsys_cs *cs = cmd_buffer->cs;
+ struct radv_winsys_cs *cs = cmd_buffer->cs;
uint32_t header = 0, command = 0;
assert(size);
@@ -1422,7 +1422,7 @@ unsigned radv_cayman_get_maxdist(int log_samples)
return max_dist[log_samples];
}
-void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int
nr_samples)
+void radv_cayman_emit_msaa_sample_locs(struct radv_winsys_cs *cs, int
nr_samples)
{
switch (nr_samples) {
default:
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
index 5c374a238d6..db7ea1f6cb4 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
@@ -37,7 +37,7 @@
#include "util/u_atomic.h"
-static void radv_amdgpu_winsys_bo_destroy(struct radeon_winsys_bo *_bo);
+static void radv_amdgpu_winsys_bo_destroy(struct radv_winsys_bo *_bo);
static void
radv_amdgpu_winsys_virtual_map(struct radv_amdgpu_winsys_bo *bo,
@@ -68,7 +68,7 @@ radv_amdgpu_winsys_virtual_unmap(struct radv_amdgpu_winsys_bo
*bo,
range->offset + bo->va, 0, AMDGPU_VA_OP_UNMAP);
if (r)
abort();
- radv_amdgpu_winsys_bo_destroy((struct radeon_winsys_bo *)range->bo);
+ radv_amdgpu_winsys_bo_destroy((struct radv_winsys_bo *)range->bo);
}
static void
@@ -99,9 +99,9 @@ radv_amdgpu_winsys_rebuild_bo_list(struct
radv_amdgpu_winsys_bo *bo)
}
static void
-radv_amdgpu_winsys_bo_virtual_bind(struct radeon_winsys_bo *_parent,
+radv_amdgpu_winsys_bo_virtual_bind(struct radv_winsys_bo *_parent,
uint64_t offset, uint64_t size,
- struct radeon_winsys_bo *_bo, uint64_t
bo_offset)
+ struct radv_winsys_bo *_bo, uint64_t
bo_offset)
{
struct radv_amdgpu_winsys_bo *parent = (struct radv_amdgpu_winsys_bo
*)_parent;
struct radv_amdgpu_winsys_bo *bo = (struct radv_amdgpu_winsys_bo*)_bo;
@@ -215,7 +215,7 @@ radv_amdgpu_winsys_bo_virtual_bind(struct radeon_winsys_bo
*_parent,
radv_amdgpu_winsys_rebuild_bo_list(parent);
}
-static void radv_amdgpu_winsys_bo_destroy(struct radeon_winsys_bo *_bo)
+static void radv_amdgpu_winsys_bo_destroy(struct radv_winsys_bo *_bo)
{
struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
@@ -253,8 +253,8 @@ static void radv_amdgpu_add_buffer_to_global_list(struct
radv_amdgpu_winsys_bo *
}
}
-static struct radeon_winsys_bo *
-radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws,
+static struct radv_winsys_bo *
+radv_amdgpu_winsys_bo_create(struct radv_winsys *_ws,
uint64_t size,
unsigned alignment,
enum radeon_bo_domain initial_domain,
@@ -295,7 +295,7 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws,
bo->ranges[0].bo_offset = 0;
radv_amdgpu_winsys_virtual_map(bo, bo->ranges);
- return (struct radeon_winsys_bo *)bo;
+ return (struct radv_winsys_bo *)bo;
}
request.alloc_size = size;
@@ -330,7 +330,7 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws,
bo->initial_domain = initial_domain;
bo->is_shared = false;
radv_amdgpu_add_buffer_to_global_list(bo);
- return (struct radeon_winsys_bo *)bo;
+ return (struct radv_winsys_bo *)bo;
error_va_map:
amdgpu_bo_free(buf_handle);
@@ -342,14 +342,14 @@ error_va_alloc:
return NULL;
}
-static uint64_t radv_amdgpu_winsys_bo_get_va(struct radeon_winsys_bo *_bo)
+static uint64_t radv_amdgpu_winsys_bo_get_va(struct radv_winsys_bo *_bo)
{
struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
return bo->va;
}
static void *
-radv_amdgpu_winsys_bo_map(struct radeon_winsys_bo *_bo)
+radv_amdgpu_winsys_bo_map(struct radv_winsys_bo *_bo)
{
struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
int ret;
@@ -361,14 +361,14 @@ radv_amdgpu_winsys_bo_map(struct radeon_winsys_bo *_bo)
}
static void
-radv_amdgpu_winsys_bo_unmap(struct radeon_winsys_bo *_bo)
+radv_amdgpu_winsys_bo_unmap(struct radv_winsys_bo *_bo)
{
struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
amdgpu_bo_cpu_unmap(bo->bo);
}
-static struct radeon_winsys_bo *
-radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws,
+static struct radv_winsys_bo *
+radv_amdgpu_winsys_bo_from_fd(struct radv_winsys *_ws,
int fd, unsigned *stride,
unsigned *offset)
{
@@ -415,7 +415,7 @@ radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws,
bo->is_shared = true;
bo->ws = ws;
radv_amdgpu_add_buffer_to_global_list(bo);
- return (struct radeon_winsys_bo *)bo;
+ return (struct radv_winsys_bo *)bo;
error_va_map:
amdgpu_va_range_free(va_handle);
@@ -428,8 +428,8 @@ error:
}
static bool
-radv_amdgpu_winsys_get_fd(struct radeon_winsys *_ws,
- struct radeon_winsys_bo *_bo,
+radv_amdgpu_winsys_get_fd(struct radv_winsys *_ws,
+ struct radv_winsys_bo *_bo,
int *fd)
{
struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
@@ -460,8 +460,8 @@ static unsigned radv_eg_tile_split_rev(unsigned
eg_tile_split)
}
static void
-radv_amdgpu_winsys_bo_set_metadata(struct radeon_winsys_bo *_bo,
- struct radeon_bo_metadata *md)
+radv_amdgpu_winsys_bo_set_metadata(struct radv_winsys_bo *_bo,
+ struct radv_bo_metadata *md)
{
struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
struct amdgpu_bo_metadata metadata = {0};
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.h
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.h
index 4512e76b333..f9c4bf5ccdd 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.h
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.h
@@ -69,7 +69,7 @@ struct radv_amdgpu_winsys_bo {
};
static inline
-struct radv_amdgpu_winsys_bo *radv_amdgpu_winsys_bo(struct radeon_winsys_bo
*bo)
+struct radv_amdgpu_winsys_bo *radv_amdgpu_winsys_bo(struct radv_winsys_bo *bo)
{
return (struct radv_amdgpu_winsys_bo *)bo;
}
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 3655e0ebd3a..bd28524efa0 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -40,19 +40,19 @@ enum {
};
struct radv_amdgpu_cs {
- struct radeon_winsys_cs base;
+ struct radv_winsys_cs base;
struct radv_amdgpu_winsys *ws;
struct amdgpu_cs_ib_info ib;
- struct radeon_winsys_bo *ib_buffer;
+ struct radv_winsys_bo *ib_buffer;
uint8_t *ib_mapped;
unsigned max_num_buffers;
unsigned num_buffers;
amdgpu_bo_handle *handles;
uint8_t *priorities;
- struct radeon_winsys_bo **old_ib_buffers;
+ struct radv_winsys_bo **old_ib_buffers;
unsigned num_old_ib_buffers;
unsigned max_num_old_ib_buffers;
unsigned *ib_size_ptr;
@@ -64,13 +64,13 @@ struct radv_amdgpu_cs {
unsigned num_virtual_buffers;
unsigned max_num_virtual_buffers;
- struct radeon_winsys_bo **virtual_buffers;
+ struct radv_winsys_bo **virtual_buffers;
uint8_t *virtual_buffer_priorities;
int *virtual_buffer_hash_table;
};
static inline struct radv_amdgpu_cs *
-radv_amdgpu_cs(struct radeon_winsys_cs *base)
+radv_amdgpu_cs(struct radv_winsys_cs *base)
{
return (struct radv_amdgpu_cs*)base;
}
@@ -101,20 +101,20 @@ static void radv_amdgpu_request_to_fence(struct
radv_amdgpu_ctx *ctx,
fence->user_ptr = (volatile uint64_t*)(ctx->fence_map + (req->ip_type *
MAX_RINGS_PER_TYPE + req->ring) * sizeof(uint64_t));
}
-static struct radeon_winsys_fence *radv_amdgpu_create_fence()
+static struct radv_winsys_fence *radv_amdgpu_create_fence()
{
struct radv_amdgpu_fence *fence = calloc(1, sizeof(struct
radv_amdgpu_fence));
- return (struct radeon_winsys_fence*)fence;
+ return (struct radv_winsys_fence*)fence;
}
-static void radv_amdgpu_destroy_fence(struct radeon_winsys_fence *_fence)
+static void radv_amdgpu_destroy_fence(struct radv_winsys_fence *_fence)
{
struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
free(fence);
}
-static bool radv_amdgpu_fence_wait(struct radeon_winsys *_ws,
- struct radeon_winsys_fence *_fence,
+static bool radv_amdgpu_fence_wait(struct radv_winsys *_ws,
+ struct radv_winsys_fence *_fence,
bool absolute,
uint64_t timeout)
{
@@ -147,7 +147,7 @@ static bool radv_amdgpu_fence_wait(struct radeon_winsys
*_ws,
return false;
}
-static void radv_amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
+static void radv_amdgpu_cs_destroy(struct radv_winsys_cs *rcs)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(rcs);
@@ -178,8 +178,8 @@ static boolean radv_amdgpu_init_cs(struct radv_amdgpu_cs
*cs,
return true;
}
-static struct radeon_winsys_cs *
-radv_amdgpu_cs_create(struct radeon_winsys *ws,
+static struct radv_winsys_cs *
+radv_amdgpu_cs_create(struct radv_winsys *ws,
enum ring_type ring_type)
{
struct radv_amdgpu_cs *cs;
@@ -226,7 +226,7 @@ radv_amdgpu_cs_create(struct radeon_winsys *ws,
return &cs->base;
}
-static void radv_amdgpu_cs_grow(struct radeon_winsys_cs *_cs, size_t min_size)
+static void radv_amdgpu_cs_grow(struct radv_winsys_cs *_cs, size_t min_size)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
@@ -309,7 +309,7 @@ static void radv_amdgpu_cs_grow(struct radeon_winsys_cs
*_cs, size_t min_size)
}
-static bool radv_amdgpu_cs_finalize(struct radeon_winsys_cs *_cs)
+static bool radv_amdgpu_cs_finalize(struct radv_winsys_cs *_cs)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
@@ -325,7 +325,7 @@ static bool radv_amdgpu_cs_finalize(struct radeon_winsys_cs
*_cs)
return !cs->failed;
}
-static void radv_amdgpu_cs_reset(struct radeon_winsys_cs *_cs)
+static void radv_amdgpu_cs_reset(struct radv_winsys_cs *_cs)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
cs->base.cdw = 0;
@@ -408,8 +408,8 @@ static void radv_amdgpu_cs_add_buffer_internal(struct
radv_amdgpu_cs *cs,
++cs->num_buffers;
}
-static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_winsys_cs *_cs,
- struct radeon_winsys_bo *bo,
+static void radv_amdgpu_cs_add_virtual_buffer(struct radv_winsys_cs *_cs,
+ struct radv_winsys_bo *bo,
uint8_t priority)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
@@ -451,8 +451,8 @@ static void radv_amdgpu_cs_add_virtual_buffer(struct
radeon_winsys_cs *_cs,
}
-static void radv_amdgpu_cs_add_buffer(struct radeon_winsys_cs *_cs,
- struct radeon_winsys_bo *_bo,
+static void radv_amdgpu_cs_add_buffer(struct radv_winsys_cs *_cs,
+ struct radv_winsys_bo *_bo,
uint8_t priority)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
@@ -466,8 +466,8 @@ static void radv_amdgpu_cs_add_buffer(struct
radeon_winsys_cs *_cs,
radv_amdgpu_cs_add_buffer_internal(cs, bo->bo, priority);
}
-static void radv_amdgpu_cs_execute_secondary(struct radeon_winsys_cs *_parent,
- struct radeon_winsys_cs *_child)
+static void radv_amdgpu_cs_execute_secondary(struct radv_winsys_cs *_parent,
+ struct radv_winsys_cs *_child)
{
struct radv_amdgpu_cs *parent = radv_amdgpu_cs(_parent);
struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
@@ -500,10 +500,10 @@ static void radv_amdgpu_cs_execute_secondary(struct
radeon_winsys_cs *_parent,
}
static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
- struct radeon_winsys_cs **cs_array,
+ struct radv_winsys_cs **cs_array,
unsigned count,
struct radv_amdgpu_winsys_bo *extra_bo,
- struct radeon_winsys_cs *extra_cs,
+ struct radv_winsys_cs *extra_cs,
amdgpu_bo_list_handle *bo_list)
{
int r;
@@ -645,13 +645,13 @@ static void radv_assign_last_submit(struct
radv_amdgpu_ctx *ctx,
request);
}
-static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
+static int radv_amdgpu_winsys_cs_submit_chained(struct radv_winsys_ctx *_ctx,
int queue_idx,
- struct radeon_winsys_cs
**cs_array,
+ struct radv_winsys_cs
**cs_array,
unsigned cs_count,
- struct radeon_winsys_cs
*initial_preamble_cs,
- struct radeon_winsys_cs
*continue_preamble_cs,
- struct radeon_winsys_fence
*_fence)
+ struct radv_winsys_cs
*initial_preamble_cs,
+ struct radv_winsys_cs
*continue_preamble_cs,
+ struct radv_winsys_fence
*_fence)
{
int r;
struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
@@ -722,13 +722,13 @@ static int radv_amdgpu_winsys_cs_submit_chained(struct
radeon_winsys_ctx *_ctx,
return r;
}
-static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx
*_ctx,
+static int radv_amdgpu_winsys_cs_submit_fallback(struct radv_winsys_ctx *_ctx,
int queue_idx,
- struct radeon_winsys_cs
**cs_array,
+ struct radv_winsys_cs
**cs_array,
unsigned cs_count,
- struct radeon_winsys_cs
*initial_preamble_cs,
- struct radeon_winsys_cs
*continue_preamble_cs,
- struct radeon_winsys_fence
*_fence)
+ struct radv_winsys_cs
*initial_preamble_cs,
+ struct radv_winsys_cs
*continue_preamble_cs,
+ struct radv_winsys_fence
*_fence)
{
int r;
struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
@@ -741,7 +741,7 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct
radeon_winsys_ctx *_ctx,
for (unsigned i = 0; i < cs_count;) {
struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[i]);
struct amdgpu_cs_ib_info ibs[AMDGPU_CS_MAX_IBS_PER_SUBMIT];
- struct radeon_winsys_cs *preamble_cs = i ? continue_preamble_cs
: initial_preamble_cs;
+ struct radv_winsys_cs *preamble_cs = i ? continue_preamble_cs :
initial_preamble_cs;
unsigned cnt = MIN2(AMDGPU_CS_MAX_IBS_PER_SUBMIT -
!!preamble_cs,
cs_count - i);
@@ -799,19 +799,19 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct
radeon_winsys_ctx *_ctx,
return 0;
}
-static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
+static int radv_amdgpu_winsys_cs_submit_sysmem(struct radv_winsys_ctx *_ctx,
int queue_idx,
- struct radeon_winsys_cs
**cs_array,
+ struct radv_winsys_cs **cs_array,
unsigned cs_count,
- struct radeon_winsys_cs
*initial_preamble_cs,
- struct radeon_winsys_cs
*continue_preamble_cs,
- struct radeon_winsys_fence
*_fence)
+ struct radv_winsys_cs
*initial_preamble_cs,
+ struct radv_winsys_cs
*continue_preamble_cs,
+ struct radv_winsys_fence *_fence)
{
int r;
struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
struct radv_amdgpu_fence *fence = (struct radv_amdgpu_fence *)_fence;
struct radv_amdgpu_cs *cs0 = radv_amdgpu_cs(cs_array[0]);
- struct radeon_winsys *ws = (struct radeon_winsys*)cs0->ws;
+ struct radv_winsys *ws = (struct radv_winsys*)cs0->ws;
amdgpu_bo_list_handle bo_list;
struct amdgpu_cs_request request;
uint32_t pad_word = 0xffff1000U;
@@ -823,8 +823,8 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct
radeon_winsys_ctx *_ctx,
for (unsigned i = 0; i < cs_count;) {
struct amdgpu_cs_ib_info ib = {0};
- struct radeon_winsys_bo *bo = NULL;
- struct radeon_winsys_cs *preamble_cs = i ? continue_preamble_cs
: initial_preamble_cs;
+ struct radv_winsys_bo *bo = NULL;
+ struct radv_winsys_cs *preamble_cs = i ? continue_preamble_cs :
initial_preamble_cs;
uint32_t *ptr;
unsigned cnt = 0;
unsigned size = 0;
@@ -905,18 +905,18 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct
radeon_winsys_ctx *_ctx,
return 0;
}
-static int radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx,
+static int radv_amdgpu_winsys_cs_submit(struct radv_winsys_ctx *_ctx,
int queue_idx,
- struct radeon_winsys_cs **cs_array,
+ struct radv_winsys_cs **cs_array,
unsigned cs_count,
- struct radeon_winsys_cs
*initial_preamble_cs,
- struct radeon_winsys_cs
*continue_preamble_cs,
- struct radeon_winsys_sem **wait_sem,
+ struct radv_winsys_cs
*initial_preamble_cs,
+ struct radv_winsys_cs
*continue_preamble_cs,
+ struct radv_winsys_sem **wait_sem,
unsigned wait_sem_count,
- struct radeon_winsys_sem **signal_sem,
+ struct radv_winsys_sem **signal_sem,
unsigned signal_sem_count,
bool can_patch,
- struct radeon_winsys_fence *_fence)
+ struct radv_winsys_fence *_fence)
{
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[0]);
struct radv_amdgpu_ctx *ctx = radv_amdgpu_ctx(_ctx);
@@ -965,7 +965,7 @@ static void *radv_amdgpu_winsys_get_cpu_addr(void *_cs,
uint64_t addr)
return ret;
}
-static void radv_amdgpu_winsys_cs_dump(struct radeon_winsys_cs *_cs,
+static void radv_amdgpu_winsys_cs_dump(struct radv_winsys_cs *_cs,
FILE* file,
uint32_t trace_id)
{
@@ -977,7 +977,7 @@ static void radv_amdgpu_winsys_cs_dump(struct
radeon_winsys_cs *_cs,
radv_amdgpu_winsys_get_cpu_addr, cs);
}
-static struct radeon_winsys_ctx *radv_amdgpu_ctx_create(struct radeon_winsys
*_ws)
+static struct radv_winsys_ctx *radv_amdgpu_ctx_create(struct radv_winsys *_ws)
{
struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
struct radv_amdgpu_ctx *ctx = CALLOC_STRUCT(radv_amdgpu_ctx);
@@ -1000,13 +1000,13 @@ static struct radeon_winsys_ctx
*radv_amdgpu_ctx_create(struct radeon_winsys *_w
ctx->fence_map = (uint64_t*)ws->base.buffer_map(ctx->fence_bo);
if (ctx->fence_map)
memset(ctx->fence_map, 0, 4096);
- return (struct radeon_winsys_ctx *)ctx;
+ return (struct radv_winsys_ctx *)ctx;
error_create:
FREE(ctx);
return NULL;
}
-static void radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
+static void radv_amdgpu_ctx_destroy(struct radv_winsys_ctx *rwctx)
{
struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
ctx->ws->base.buffer_destroy(ctx->fence_bo);
@@ -1014,7 +1014,7 @@ static void radv_amdgpu_ctx_destroy(struct
radeon_winsys_ctx *rwctx)
FREE(ctx);
}
-static bool radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx,
+static bool radv_amdgpu_ctx_wait_idle(struct radv_winsys_ctx *rwctx,
enum ring_type ring_type, int ring_index)
{
struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
@@ -1032,7 +1032,7 @@ static bool radv_amdgpu_ctx_wait_idle(struct
radeon_winsys_ctx *rwctx,
return true;
}
-static struct radeon_winsys_sem *radv_amdgpu_create_sem(struct radeon_winsys
*_ws)
+static struct radv_winsys_sem *radv_amdgpu_create_sem(struct radv_winsys *_ws)
{
int ret;
amdgpu_semaphore_handle sem;
@@ -1040,10 +1040,10 @@ static struct radeon_winsys_sem
*radv_amdgpu_create_sem(struct radeon_winsys *_w
ret = amdgpu_cs_create_semaphore(&sem);
if (ret)
return NULL;
- return (struct radeon_winsys_sem *)sem;
+ return (struct radv_winsys_sem *)sem;
}
-static void radv_amdgpu_destroy_sem(struct radeon_winsys_sem *_sem)
+static void radv_amdgpu_destroy_sem(struct radv_winsys_sem *_sem)
{
amdgpu_semaphore_handle sem = (amdgpu_semaphore_handle)_sem;
amdgpu_cs_destroy_semaphore(sem);
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.h
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.h
index 41d0b2f2efb..90d37bc2409 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.h
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.h
@@ -53,12 +53,12 @@ struct radv_amdgpu_ctx {
amdgpu_context_handle ctx;
struct radv_amdgpu_fence last_submission[AMDGPU_HW_IP_DMA +
1][MAX_RINGS_PER_TYPE];
- struct radeon_winsys_bo *fence_bo;
+ struct radv_winsys_bo *fence_bo;
uint64_t *fence_map;
};
static inline struct radv_amdgpu_ctx *
-radv_amdgpu_ctx(struct radeon_winsys_ctx *base)
+radv_amdgpu_ctx(struct radv_winsys_ctx *base)
{
return (struct radv_amdgpu_ctx *)base;
}
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
index eaa978e3850..134151cc381 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
@@ -76,7 +76,7 @@ static int radv_amdgpu_surface_sanity(const struct
ac_surf_info *surf_info,
return 0;
}
-static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
+static int radv_amdgpu_winsys_surface_init(struct radv_winsys *_ws,
const struct ac_surf_info *surf_info,
struct radeon_surf *surf)
{
@@ -100,7 +100,7 @@ static int radv_amdgpu_winsys_surface_init(struct
radeon_winsys *_ws,
return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf);
}
-static int radv_amdgpu_winsys_surface_best(struct radeon_winsys *rws,
+static int radv_amdgpu_winsys_surface_best(struct radv_winsys *rws,
struct radeon_surf *surf)
{
return 0;
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
index c7688cf4c9b..9dd51384c7e 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
@@ -66,13 +66,13 @@ do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
return true;
}
-static void radv_amdgpu_winsys_query_info(struct radeon_winsys *rws,
+static void radv_amdgpu_winsys_query_info(struct radv_winsys *rws,
struct radeon_info *info)
{
*info = ((struct radv_amdgpu_winsys *)rws)->info;
}
-static void radv_amdgpu_winsys_destroy(struct radeon_winsys *rws)
+static void radv_amdgpu_winsys_destroy(struct radv_winsys *rws)
{
struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys*)rws;
@@ -81,7 +81,7 @@ static void radv_amdgpu_winsys_destroy(struct radeon_winsys
*rws)
FREE(rws);
}
-struct radeon_winsys *
+struct radv_winsys *
radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, uint64_t
perftest_flags)
{
uint32_t drm_major, drm_minor, r;
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h
index 2d9cf248389..660e626a489 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h
@@ -35,7 +35,7 @@
#include "util/list.h"
struct radv_amdgpu_winsys {
- struct radeon_winsys base;
+ struct radv_winsys base;
amdgpu_device_handle dev;
struct radeon_info info;
@@ -52,7 +52,7 @@ struct radv_amdgpu_winsys {
};
static inline struct radv_amdgpu_winsys *
-radv_amdgpu_winsys(struct radeon_winsys *base)
+radv_amdgpu_winsys(struct radv_winsys *base)
{
return (struct radv_amdgpu_winsys*)base;
}
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys_public.h
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys_public.h
index 854e216551f..394c60df435 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys_public.h
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys_public.h
@@ -29,7 +29,7 @@
#ifndef RADV_AMDGPU_WINSYS_PUBLIC_H
#define RADV_AMDGPU_WINSYS_PUBLIC_H
-struct radeon_winsys *radv_amdgpu_winsys_create(int fd, uint64_t debug_flags,
+struct radv_winsys *radv_amdgpu_winsys_create(int fd, uint64_t debug_flags,
uint64_t perftest_flags);
#endif /* RADV_AMDGPU_WINSYS_PUBLIC_H */
--
2.13.0
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