On Tue, 13 Dec 2011 15:35:20 -0800, Paul Berry <stereotype...@gmail.com> wrote: > Previous to this patch, the function intel_batchbuffer_emit_mi_flush() > was a bit of a misnomer. On Gen4+, when not using the blit engine, it > didn't actually flush the pipeline--it simply generated a > _3DSTATE_PIPE_CONTROL command with the necessary bits set to flush GPU > caches. This was usually sufficient, since in most situations where > intel_batchbuffer_emit_mi_flush() wass called, all we really care > about was ensuring cache coherency.
I think I've validated that the set of workarounds doesn't change when adding the CS stall bit. Reviewed-by: Eric Anholt <e...@anholt.net>
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