On Wed, May 10, 2017 at 9:36 PM, Nils Wallménius
<nils.wallmen...@gmail.com> wrote:
> Hi Marek,
>
> A comment below
>
> Den 10 maj 2017 20:29 skrev "Marek Olšák" <mar...@gmail.com>:
>
> From: Marek Olšák <marek.ol...@amd.com>
>
> Cc: 17.1 <mesa-sta...@lists.freedesktop.org>
> Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
> ---
> src/amd/addrlib/gfx9/gfx9addrlib.cpp | 57
> ++++++++++++++++++++++++++++++++++++
> src/amd/addrlib/gfx9/gfx9addrlib.h | 8 +++--
> src/amd/common/amdgpu_id.h | 10 +++++++
> 3 files changed, 72 insertions(+), 3 deletions(-)
>
> diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> index 96b05de..9b25371 100644
> --- a/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> +++ b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> @@ -1186,20 +1186,34 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
> if (m_settings.isVega10)
> {
> m_settings.isDce12 = 1;
> }
>
> m_settings.metaBaseAlignFix = 1;
>
> m_settings.depthPipeXorDisable = 1;
> break;
>
> + case FAMILY_RV:
> + m_settings.isArcticIsland = 1;
> + m_settings.isRaven = ASICREV_IS_RAVEN(uChipRevision);
> +
> + if (m_settings.isRaven)
> + {
> + m_settings.isDcn1 = 1;
> + }
> +
> + m_settings.metaBaseAlignFix = 1;
> +
> + m_settings.depthPipeXorDisable = 1;
> + break;
> +
> default:
> ADDR_ASSERT(!"This should be a Fusion");
> break;
> }
>
> return family;
> }
>
> /**
>
> ************************************************************************************************************************
> @@ -2727,20 +2741,49 @@ BOOL_32 Gfx9Lib::IsValidDisplaySwizzleMode(
> case ADDR_SW_64KB_R_X:
> case ADDR_SW_VAR_D_X:
> case ADDR_SW_VAR_R_X:
> support = (pIn->bpp <= 64);
> break;
>
> default:
> break;
> }
> }
> + else if (m_settings.isDcn1)
> + {
> + switch (swizzleMode)
> + {
> + case ADDR_SW_4KB_D:
> + case ADDR_SW_64KB_D:
> + case ADDR_SW_VAR_D:
> + case ADDR_SW_64KB_D_T:
> + case ADDR_SW_4KB_D_X:
> + case ADDR_SW_64KB_D_X:
> + case ADDR_SW_VAR_D_X:
> + support = (pIn->bpp == 64);
> + break;
> +
> + case ADDR_SW_LINEAR:
> + case ADDR_SW_4KB_S:
> + case ADDR_SW_64KB_S:
> + case ADDR_SW_VAR_S:
> + case ADDR_SW_64KB_S_T:
> + case ADDR_SW_4KB_S_X:
> + case ADDR_SW_64KB_S_X:
> + case ADDR_SW_VAR_S_X:
> + support = (pIn->bpp <= 64);
> + break;
> +
> + default:
> + break;
> + }
> + }
> else
> {
> ADDR_NOT_IMPLEMENTED();
> }
>
> return support;
> }
>
> /**
>
> ************************************************************************************************************************
> @@ -3188,20 +3231,34 @@ ADDR_E_RETURNCODE
> Gfx9Lib::HwlGetPreferredSurfaceSetting(
> else if (m_settings.isDce12)
> {
> if (pIn->bpp != 32)
> {
> blockSet.micro = FALSE;
> }
>
> // DCE12 does not support display surface to be _T
> swizzle mode
> prtXor = FALSE;
> }
> + else if (m_settings.isDcn1)
> + {
> + // _R is not supported by Dcn1
> + if (pIn->bpp == 64)
> + {
> + swType = ADDR_SW_D;
> + }
> + else
> + {
> + swType = ADDR_SW_S;
> + }
> +
> + blockSet.micro = FALSE;
> + }
> else
> {
> ADDR_NOT_IMPLEMENTED();
> returnCode = ADDR_NOTSUPPORTED;
> }
> }
> }
> }
>
> if ((numFrags > 1) &&
> diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.h
> b/src/amd/addrlib/gfx9/gfx9addrlib.h
> index 73d51f1..9623610 100644
> --- a/src/amd/addrlib/gfx9/gfx9addrlib.h
> +++ b/src/amd/addrlib/gfx9/gfx9addrlib.h
> @@ -47,25 +47,27 @@ namespace V2
> * @brief GFX9 specific settings structure.
>
> ************************************************************************************************************************
> */
> struct Gfx9ChipSettings
> {
> struct
> {
> // Asic/Generation name
> UINT_32 isArcticIsland : 1;
> UINT_32 isVega10 : 1;
> - UINT_32 reserved0 : 30;
> + UINT_32 isRaven : 1;
> + UINT_32 reserved0 : 29;
>
> // Display engine IP version name
> UINT_32 isDce12 : 1;
> - UINT_32 reserved1 : 31;
> + UINT_32 isDcn1 : 1;
> + UINT_32 reserved1 : 29;
>
>
> The above reserved1 should be 30 bits to make an even 32, not sure it
> matters but looks off.
Yeah it doesn't matter. I'll fix that.
Marek
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