From: Marek Olšák <marek.ol...@amd.com>
Cc: 17.1 <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
---
src/amd/addrlib/gfx9/gfx9addrlib.cpp | 57 ++++++++++++++++++++++++++++++++++++
src/amd/addrlib/gfx9/gfx9addrlib.h | 8 +++--
src/amd/common/amdgpu_id.h | 10 +++++++
3 files changed, 72 insertions(+), 3 deletions(-)
diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.cpp
b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
index 96b05de..9b25371 100644
--- a/src/amd/addrlib/gfx9/gfx9addrlib.cpp
+++ b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
@@ -1186,20 +1186,34 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
if (m_settings.isVega10)
{
m_settings.isDce12 = 1;
}
m_settings.metaBaseAlignFix = 1;
m_settings.depthPipeXorDisable = 1;
break;
+ case FAMILY_RV:
+ m_settings.isArcticIsland = 1;
+ m_settings.isRaven = ASICREV_IS_RAVEN(uChipRevision);
+
+ if (m_settings.isRaven)
+ {
+ m_settings.isDcn1 = 1;
+ }
+
+ m_settings.metaBaseAlignFix = 1;
+
+ m_settings.depthPipeXorDisable = 1;
+ break;
+
default:
ADDR_ASSERT(!"This should be a Fusion");
break;
}
return family;
}
/**
************************************************************************************************************************
@@ -2727,20 +2741,49 @@ BOOL_32 Gfx9Lib::IsValidDisplaySwizzleMode(
case ADDR_SW_64KB_R_X:
case ADDR_SW_VAR_D_X:
case ADDR_SW_VAR_R_X:
support = (pIn->bpp <= 64);
break;
default:
break;
}
}
+ else if (m_settings.isDcn1)
+ {
+ switch (swizzleMode)
+ {
+ case ADDR_SW_4KB_D:
+ case ADDR_SW_64KB_D:
+ case ADDR_SW_VAR_D:
+ case ADDR_SW_64KB_D_T:
+ case ADDR_SW_4KB_D_X:
+ case ADDR_SW_64KB_D_X:
+ case ADDR_SW_VAR_D_X:
+ support = (pIn->bpp == 64);
+ break;
+
+ case ADDR_SW_LINEAR:
+ case ADDR_SW_4KB_S:
+ case ADDR_SW_64KB_S:
+ case ADDR_SW_VAR_S:
+ case ADDR_SW_64KB_S_T:
+ case ADDR_SW_4KB_S_X:
+ case ADDR_SW_64KB_S_X:
+ case ADDR_SW_VAR_S_X:
+ support = (pIn->bpp <= 64);
+ break;
+
+ default:
+ break;
+ }
+ }
else
{
ADDR_NOT_IMPLEMENTED();
}
return support;
}
/**
************************************************************************************************************************
@@ -3188,20 +3231,34 @@ ADDR_E_RETURNCODE
Gfx9Lib::HwlGetPreferredSurfaceSetting(
else if (m_settings.isDce12)
{
if (pIn->bpp != 32)
{
blockSet.micro = FALSE;
}
// DCE12 does not support display surface to be _T
swizzle mode
prtXor = FALSE;
}
+ else if (m_settings.isDcn1)
+ {
+ // _R is not supported by Dcn1
+ if (pIn->bpp == 64)
+ {
+ swType = ADDR_SW_D;
+ }
+ else
+ {
+ swType = ADDR_SW_S;
+ }
+
+ blockSet.micro = FALSE;
+ }
else
{
ADDR_NOT_IMPLEMENTED();
returnCode = ADDR_NOTSUPPORTED;
}
}
}
}
if ((numFrags > 1) &&
diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.h
b/src/amd/addrlib/gfx9/gfx9addrlib.h
index 73d51f1..9623610 100644
--- a/src/amd/addrlib/gfx9/gfx9addrlib.h
+++ b/src/amd/addrlib/gfx9/gfx9addrlib.h
@@ -47,25 +47,27 @@ namespace V2
* @brief GFX9 specific settings structure.
************************************************************************************************************************
*/
struct Gfx9ChipSettings
{
struct
{
// Asic/Generation name
UINT_32 isArcticIsland : 1;
UINT_32 isVega10 : 1;
- UINT_32 reserved0 : 30;
+ UINT_32 isRaven : 1;
+ UINT_32 reserved0 : 29;
// Display engine IP version name
UINT_32 isDce12 : 1;
- UINT_32 reserved1 : 31;
+ UINT_32 isDcn1 : 1;
+ UINT_32 reserved1 : 29;
// Misc configuration bits
UINT_32 metaBaseAlignFix : 1;
UINT_32 depthPipeXorDisable : 1;
UINT_32 reserved2 : 30;
};
};
/**
************************************************************************************************************************
@@ -194,21 +196,21 @@ protected:
AddrResourceType rsrcType,
AddrSwizzleMode swMode,
UINT_32 elementBytesLog2) const;
virtual UINT_32 HwlComputeSurfaceBaseAlign(AddrSwizzleMode swizzleMode)
const
{
UINT_32 baseAlign;
if (IsXor(swizzleMode))
{
- if (m_settings.isVega10)
+ if (m_settings.isVega10 || m_settings.isRaven)
{
baseAlign = GetBlockSize(swizzleMode);
}
else
{
UINT_32 blockSizeLog2 = GetBlockSizeLog2(swizzleMode);
UINT_32 pipeBits = GetPipeXorBits(blockSizeLog2);
UINT_32 bankBits = GetBankXorBits(blockSizeLog2);
baseAlign = 1 << (Min(blockSizeLog2, m_pipeInterleaveLog2 +
pipeBits+ bankBits));
}
diff --git a/src/amd/common/amdgpu_id.h b/src/amd/common/amdgpu_id.h
index 316b30f..6f254f0 100644
--- a/src/amd/common/amdgpu_id.h
+++ b/src/amd/common/amdgpu_id.h
@@ -42,20 +42,21 @@
enum {
FAMILY_UNKNOWN,
FAMILY_SI,
FAMILY_CI,
FAMILY_KV,
FAMILY_VI,
FAMILY_CZ,
FAMILY_PI,
FAMILY_AI,
+ FAMILY_RV,
FAMILY_LAST,
};
/* SI specific rev IDs */
enum {
SI_TAHITI_P_A11 = 1,
SI_TAHITI_P_A0 = SI_TAHITI_P_A11, /*A0 is alias of A11*/
SI_TAHITI_P_A21 = 5,
SI_TAHITI_P_B0 = SI_TAHITI_P_A21, /*B0 is alias of A21*/
SI_TAHITI_P_A22 = 6,
@@ -178,11 +179,20 @@ enum {
/* AI specific rev IDs */
enum {
AI_VEGA10_P_A0 = 0x01,
AI_UNKNOWN = 0xFF
};
#define ASICREV_IS_VEGA10_P(eChipRev) \
((eChipRev) >= AI_VEGA10_P_A0 && (eChipRev) < AI_UNKNOWN)
+/* RV specific rev IDs */
+enum {
+ RAVEN_A0 = 0x01,
+ RAVEN_UNKNOWN = 0xFF
+};
+
+#define ASICREV_IS_RAVEN(eChipRev) \
+ ((eChipRev) >= RAVEN_A0 && (eChipRev) < RAVEN_UNKNOWN)
+
#endif /* AMDGPU_ID_H */
--
2.7.4
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