This fixes issues seen when adding support for full 48-bit addresses.
The 48-bit addresses themselves have nothing to do with it other than
that it caused the kernel to place buffers slightly differently so they
interacted differently with the caches.
Cc: "13.0 17.0" <mesa-sta...@lists.freedesktop.org>
---
src/intel/vulkan/genX_blorp_exec.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/genX_blorp_exec.c
b/src/intel/vulkan/genX_blorp_exec.c
index 1d07fd7..402f6d2 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -115,8 +115,20 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch,
uint32_t size,
struct blorp_address *addr)
{
struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
+
+ /* From the Sky Lake PRM, 3DSTATE_VERTEX_BUFFERS:
+ *
+ * "The VF cache needs to be invalidated before binding and then using
+ * Vertex Buffers that overlap with any previously bound Vertex Buffer
+ * (at a 64B granularity) since the last invalidation. A VF cache
+ * invalidate is performed by setting the "VF Cache Invalidation Enable"
+ * bit in PIPE_CONTROL."
+ *
+ * In order to avoid this problem, we align all vertex buffer allocations
+ * to 64 bytes.
+ */
struct anv_state vb_state =
- anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 16);
+ anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 64);
*addr = (struct blorp_address) {
.buffer = &cmd_buffer->device->dynamic_state_block_pool.bo,
--
2.5.0.400.gff86faf
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