Actually nevermind.
Patches 1-3:
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Patches 4-5:
These have no effect, because r600g hw doesn't use TC for index fetches.
Marek
On Tue, Mar 28, 2017 at 9:33 PM, Marek Olšák <mar...@gmail.com> wrote:
> BTW, I don't know if tcc_cache_line_size has the correct value for
> pre-GCN chips.
>
> Marek
>
> On Sun, Mar 26, 2017 at 5:36 PM, Constantine Kharlamov
> <hi-an...@yandex.ru> wrote:
>> Stolen from radeonsi
>>
>> Signed-off-by: Constantine Kharlamov <hi-an...@yandex.ru>
>> ---
>> src/gallium/drivers/r600/r600_state_common.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/drivers/r600/r600_state_common.c
>> b/src/gallium/drivers/r600/r600_state_common.c
>> index 961e04e9db..5293c4034f 100644
>> --- a/src/gallium/drivers/r600/r600_state_common.c
>> +++ b/src/gallium/drivers/r600/r600_state_common.c
>> @@ -1766,7 +1766,8 @@ static void r600_draw_vbo(struct pipe_context *ctx,
>> const struct pipe_draw_info
>> info->instance_count > 1 ||
>> info->count*ib.index_size >
>> 20)) {
>> u_upload_data(ctx->stream_uploader, 0,
>> - info->count * ib.index_size, 256,
>> + info->count * ib.index_size,
>> +
>> rctx->screen->b.info.tcc_cache_line_size,
>> ib.user_buffer, &ib.offset,
>> &ib.buffer);
>> ib.user_buffer = NULL;
>> }
>> --
>> 2.12.0
>>
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