On Wed, Mar 1, 2017 at 10:35 AM, Emil Velikov <emil.l.veli...@gmail.com> wrote:
> Hello list, > > The candidate for the Mesa 17.0.1 is now available. Currently we have: > - 60 queued > - 9 nominated (outstanding) > - and 0 rejected patch(es) > > > The current queue consists of: > > On the GLX/EGL front we have a GLVND fix for "The Binding of Isaac: > Rebirth" > and other games, eglQuerySurface now returns correct geometry when running > under X11/DRI3. > > There's a number of crash fixes affecting all Gallium drivers. An old > regression fix for r300 on BE hardware been fixed. The radeonsi driver has > fixes for Tessellation shaders on Carrizo and Stoney hardware. > > While on the nouveau side, compute shader have been improved on some > nvc0 devices. > > The vc4 and etnaviv drivers have also seen a couple of small fixe. > > For the Intel drivers (both GL and Vulkan) we have a diverse bunch of > patches - > from CTS fixes for Sandy Bridge, to improved swizzle clears and improved > handling of GPUs without (Last Level Cache) LLC. > > On integration side - we had some Android build fixes and a new script to > parse and look for bug fixes. > > > And for those of you wondering - the delay was caused by a buggy > optimisation > pass, that has since been removed. > I don't see the remove patch on the queue below. > > Take a look at section "Mesa stable queue" for more information. > > > Testing reports/general approval > -------------------------------- > Any testing reports (or general approval of the state of the branch) will > be > greatly appreciated. > > The plan is to have 17.0.1 this Friday (3th of March), around or shortly > after 19:00 GMT. > > If you have any questions or suggestions - be that about the current patch > queue or otherwise, please go ahead. > > > Trivial merge conflicts > ----------------------- > commit 9c80a8133f8e75d95bad54bae92402fa7a7252e0 > Author: Marek Olšák <marek.ol...@amd.com> > > radeonsi: fix UNSIGNED_BYTE index buffer fallback with non-zero start > (v2) > > (cherry picked from commit a264fee6245856340fab9024e1a428626e966335) > > > Marek, the above commit seems to imply 791e8ce04a7e9970f437858bdff0a1 > f8b47626ba. > Can you please let me know if we should pick the latter as well ? > > commit b8d23715f548afe7a700c2d8eb59e806e7bcf083 > Author: Nicolai Hähnle <nicolai.haeh...@amd.com> > > winsys/amdgpu: reduce max_alloc_size based on GTT limits > > (cherry picked from commit 550125e1e73e2441989da11495057a20dd9dad44) > > > commit 0a8df0685e7a9d6db3a1765a9de701565c759493 > Author: Leo Liu <leo....@amd.com> > > configure.ac: check require_basic_egl only if egl enabled > > (cherry picked from commit 5398d006de3d2bd668e3fc4b80a3de0c101a3e43) > > > > Cheers, > Emil > > > Mesa stable queue > ----------------- > > Nominated (9) > ============= > > Jason Ekstrand (2): > d49d275 anv/blorp: Don't sanitize the swizzle for blorp_clear > 42b10b1 anv/blorp/clear_subpass: Only set surface clear color > for fast clears > > Marek Olšák (2): > a40b761 st/mesa: reset sample_mask, min_sample, and > render_condition for PBO ops > cc2f92b st/mesa: set blend state for PBO readbacks > > Samuel Iglesias Gonsálvez (5): > 7427425 i965/fs: mark last DF uniform array element as 64 bit live > one > a497ab6 i965/fs: detect different bit size accesses to uniforms > to push them in proper locations > 56266df i965/fs: fix indirect load DF uniforms on BSW/BXT > d812212 i965/fs: fix source type when emitting MOV_INDIRECT to > read ICP handles > 0dddad5 i965/fs: emit MOV_INDIRECT with the source with the > right register type > > > Queued (60) > =========== > > Bas Nieuwenhuizen (4): > radv: Never try to create more than max_sets descriptor sets. > radv: Reset emitted compute pipeline when calling secondary cmd > buffer. > radv: Only use PKT3_OCCLUSION_QUERY when it doesn't hang. > radv: Use correct size for availability flag. > > Ben Crocker (3): > gallivm: Reenable PPC VSX (v3) > gallivm: Improve debug output (V2) > gallivm: Override getHostCPUName() "generic" w/ "pwr8" (v4) > > Brendan King (1): > egl/dri3: implement query surface hook > > Christian Gmeiner (2): > etnaviv: move pctx initialisation to avoid a null dereference > etnaviv: remove number of pixel pipes validation > > Connor Abbott (1): > anv: fix Get*MemoryRequirements for !LLC > > Dave Airlie (6): > tgsi: fix memory leak in tgsi sanity check > radv: change base aligmment for allocated memory. > radv: fix cik macroModeIndex. > radv: adopt some init config workarounds from radeonsi. > radv: fix depth format in blit2d. > radv: fix txs for sampler buffers > > Emil Velikov (6): > bin/get-extra-pick-list: use git merge-base to get the branchpoint > bin/get-extra-pick-list: rework to use already_picked list > bin/get-typod-pick-list.sh: limit `git grep ...' to only as needed > bin/get-pick-list.sh: limit `git grep ...' only as needed > bin/get-pick-list.sh: remove ancient way of nominating patches > bin/get-fixes-pick-list.sh: add new script > > Eric Anholt (1): > vc4: Avoid emitting small immediates for UBO indirect load address > guards. > > Grazvydas Ignotas (3): > r300g: only allow byteswapped formats on big endian > gallium/u_queue: fix a crash with atexit handlers > gallium/u_queue: set num_threads correctly if not all threads start > > Hans de Goede (1): > glx/glvnd: Fix GLXdispatchIndex sorting > > Ilia Mirkin (4): > gm107/ir: fix address offset bitfield for ATOMS > nvc0: set the render condition in the compute object > st/mesa: don't pass compare mode for stencil-sampled textures > nvc0: disable linked tsc mode in compute launch descriptor > > Jason Ekstrand (10): > i965/sampler_state: Clamp min/max LOD to 14 on gen7+ > i965/sampler_state: Pass texObj into update_sampler_state > i965/sampler_state: Set the "Base Mip Level" field on Sandy Bridge > intel/blorp: Swizzle clear colors on the CPU > i965/fs: Fix the inline nir_op_pack_double optimization > anv: Add an invalidate_range helper > anv/query: clflush the bo map on non-LLC platforms > genxml: Make MI_STORE_DATA_IMM more consistent > anv/query: Perform CmdResetQueryPool on the GPU > intel/blorp: Explicitly flush all allocated state > > Jose Maria Casanova Crespo (1): > glsl: non-last member unsized array on SSBO must fail > compilation on GLSL ES 3.1 > > Kenneth Graunke (1): > mesa: Do (TCS && !TES) draw time validation in ES as well. > > Leo Liu (1): > configure.ac: check require_basic_egl only if egl enabled > > Lionel Landwerlin (2): > anv: wsi: report presentation error per image request > i965/fs: fix uninitialized memory access > > Marek Olšák (6): > radeonsi: fix UNSIGNED_BYTE index buffer fallback with non-zero > start (v2) > gallium/util: remove unused u_index_modify helpers > gallium/u_index_modify: don't add PIPE_TRANSFER_UNSYNCHRONIZED > unconditionally > gallium/u_queue: fix random crashes when the app calls exit() > radeonsi: fix broken tessellation on Carrizo and Stoney > amd/common: fix ASICREV_IS_POLARIS11_M for Polaris12 > > Mauro Rossi (2): > android: radeonsi: fix sid_table.h generated header include path > android: glsl: build shader cache sources > > Nicolai Hähnle (3): > winsys/amdgpu: reduce max_alloc_size based on GTT limits > radeonsi: handle MultiDrawIndirect in si_get_draw_start_count > radeonsi: fix UINT/SINT clamping for 10-bit formats on <= CIK > > Samuel Iglesias Gonsálvez (1): > glsl: fix heap-use-after-free in ast_declarator_list::hir() > > Tapani Pälli (1): > android: fix droid_create_image_from_prime_fd_yuv for YV12 > > > Rejected (0) > ============ > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev >
_______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
