[Mesa-dev] [PATCH v3 18/24] i965/vec4: adapt setup_imm_df() to allow inserting instructions before another one

[Samuel Iglesias Gonsálvez]

Add a new setup_imm_df() that allows the insertion of the instructions
before another one. This will be used in the lowering passes for DF
instructions.

v2:
- Adapt emission of DIM instruction too.

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
---
 src/mesa/drivers/dri/i965/brw_vec4.h       |  2 ++
 src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 26 +++++++++++++++++++++-----
 2 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 29b203af89e..01b928ef4a7 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -328,6 +328,8 @@ public:
                                   brw_reg_type single_type);
 
    src_reg setup_imm_df(double v);
+   src_reg setup_imm_df(double v, struct bblock_t *block,
+                        vec4_instruction *inst);
 
    vec4_instruction *shuffle_64bit_data(dst_reg dst, src_reg src,
                                         bool for_write,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 2127415be7a..e99db2cef8e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -1213,6 +1213,12 @@ vec4_visitor::emit_conversion_to_double(dst_reg dst, 
src_reg src,
 src_reg
 vec4_visitor::setup_imm_df(double v)
 {
+   return setup_imm_df(v, NULL, NULL);
+}
+
+src_reg
+vec4_visitor::setup_imm_df(double v, struct bblock_t *block, 
brw::vec4_instruction *inst)
+{
    assert(devinfo->gen >= 7);
 
    if (devinfo->gen >= 8)
@@ -1223,7 +1229,10 @@ vec4_visitor::setup_imm_df(double v)
     */
    if (devinfo->is_haswell) {
       dst_reg dst = retype(dst_reg(VGRF, alloc.allocate(2)), 
BRW_REGISTER_TYPE_DF);
-      emit(DIM(dst, brw_imm_df(v)))->force_writemask_all = true;
+      if (block)
+         emit_before(block, inst, DIM(dst, 
brw_imm_df(v)))->force_writemask_all = true;
+      else
+         emit(DIM(dst, brw_imm_df(v)))->force_writemask_all = true;
       return swizzle(src_reg(retype(dst, BRW_REGISTER_TYPE_DF)), 
BRW_SWIZZLE_XXXX);
    }
 
@@ -1248,10 +1257,17 @@ vec4_visitor::setup_imm_df(double v)
    const dst_reg tmp =
       retype(dst_reg(VGRF, alloc.allocate(2)), BRW_REGISTER_TYPE_UD);
    for (int n = 0; n < 2; n++) {
-      emit(MOV(writemask(offset(tmp, 8, n), WRITEMASK_X), brw_imm_ud(di.i1)))
-         ->force_writemask_all = true;
-      emit(MOV(writemask(offset(tmp, 8, n), WRITEMASK_Y), brw_imm_ud(di.i2)))
-         ->force_writemask_all = true;
+      if (block) {
+         emit_before(block, inst, MOV(writemask(offset(tmp, 8, n), 
WRITEMASK_X), brw_imm_ud(di.i1)))
+            ->force_writemask_all = true;
+         emit_before(block, inst, MOV(writemask(offset(tmp, 8, n), 
WRITEMASK_Y), brw_imm_ud(di.i2)))
+            ->force_writemask_all = true;
+      } else {
+         emit(MOV(writemask(offset(tmp, 8, n), WRITEMASK_X), 
brw_imm_ud(di.i1)))
+            ->force_writemask_all = true;
+         emit(MOV(writemask(offset(tmp, 8, n), WRITEMASK_Y), 
brw_imm_ud(di.i2)))
+            ->force_writemask_all = true;
+      }
    }
 
    return swizzle(src_reg(retype(tmp, BRW_REGISTER_TYPE_DF)), 
BRW_SWIZZLE_XXXX);
-- 
2.11.0

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