The hardware applies the same channel enable signals to both halves of
the compressed instruction which will be just wrong under non-uniform
control flow. Fix this by splitting those instructions to SIMD4.
Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Reviewed-by: Francisco Jerez <curroje...@riseup.net>
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 5c405709127..0099ae264b2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -4579,6 +4579,15 @@ get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo,
*/
if (channels_per_grf != (exec_type_size == 8 ? 4 : 8))
max_width = MIN2(max_width, channels_per_grf);
+
+ /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
+ * because HW applies the same channel enable signals to both halves of
+ * the compressed instruction which will be just wrong under
+ * non-uniform control flow.
+ */
+ if (devinfo->gen == 7 && !devinfo->is_haswell &&
+ (exec_type_size == 8 || type_sz(inst->dst.type) == 8))
+ max_width = MIN2(max_width, 4);
}
/* Only power-of-two execution sizes are representable in the instruction
--
2.11.0
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