Then the SIMD lowering pass will get rid of any compressed instructions with
scalar
source (whether force_writemask_all or not) and we avoid hitting the Gen7 region
decompression bug.
Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com>
Suggested-by: Francisco Jerez <curroje...@riseup.net>
Reviewed-by: Francisco Jerez <curroje...@riseup.net>
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 9fb5dabe6f3..8d5b381f4a1 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -4510,11 +4510,16 @@ get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo,
*/
if (devinfo->gen < 8) {
for (unsigned i = 0; i < inst->sources; i++) {
+ /* IVB implements DF scalars as <0;2,1> regions. */
+ const bool is_scalar_exception = is_uniform(inst->src[i]) &&
+ (devinfo->is_haswell || type_sz(inst->src[i].type) != 8);
+ const bool is_packed_word_exception =
+ type_sz(inst->dst.type) == 4 && inst->dst.stride == 1 &&
+ type_sz(inst->src[i].type) == 2 && inst->src[i].stride == 1;
+
if (inst->size_written > REG_SIZE &&
inst->size_read(i) != 0 && inst->size_read(i) <= REG_SIZE &&
- !is_uniform(inst->src[i]) &&
- !(type_sz(inst->dst.type) == 4 && inst->dst.stride == 1 &&
- type_sz(inst->src[i].type) == 2 && inst->src[i].stride == 1)) {
+ !is_scalar_exception && !is_packed_word_exception) {
const unsigned reg_count = DIV_ROUND_UP(inst->size_written,
REG_SIZE);
max_width = MIN2(max_width, inst->exec_size / reg_count);
}
--
2.11.0
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