On Tue, Jan 17, 2017 at 03:17:08PM -0800, Jason Ekstrand wrote:
> I think the commit message could use some work. How about:
> i965/blorp: Use the render cache mechanism instead of explicit flusing
Sounds good, thanks!
> On Tue, Jan 17, 2017 at 10:48 AM, Topi Pohjolainen
> <[1]topi.pohjolai...@gmail.com> wrote:
>
> by replacing brw_emit_mi_flush() with brw_render_cache_set_check_
> flush().
> The latter splits the flush in two:
> brw_emit_pipe_control_flush(brw,
> PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> PIPE_CONTROL_RENDER_TARGET_FLUSH |
> PIPE_CONTROL_CS_STALL);
> brw_emit_pipe_control_flush(brw,
> PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
> |
> PIPE_CONTROL_CONST_CACHE_INVALIDATE);
> instead of
> int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_
> FLUSH;
> if (brw->gen >= 6) {
> flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
> PIPE_CONTROL_CONST_CACHE_INVALIDATE |
> PIPE_CONTROL_DEPTH_CACHE_FLUSH |
> PIPE_CONTROL_VF_CACHE_INVALIDATE |
> PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
> PIPE_CONTROL_CS_STALL;
> }
> brw_emit_pipe_control_flush(brw, flags);
> Signed-off-by: Topi Pohjolainen <[2]topi.pohjolai...@intel.com>
> ---
> src/mesa/drivers/dri/i965/genX_blorp_exec.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
> diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> index bb1dfa9..c0cbde5 100644
> --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
> @@ -25,6 +25,7 @@
> #include "intel_batchbuffer.h"
> #include "intel_mipmap_tree.h"
> +#include "intel_fbo.h"
> #include "brw_context.h"
> #include "brw_state.h"
> @@ -179,7 +180,9 @@ genX(blorp_exec)(struct blorp_batch *batch,
> * data with different formats, which blorp does for stencil and
> depth
> * data.
> */
> - brw_emit_mi_flush(brw);
> + if (params->src.enabled)
> + brw_render_cache_set_check_flush(brw,
> params->src.addr.buffer);
> + brw_render_cache_set_check_flush(brw, params->dst.addr.buffer);
> brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
> @@ -256,6 +259,8 @@ retry:
> brw->no_depth_or_stencil = false;
> brw->ib.type = -1;
> + brw_render_cache_set_add_bo(brw, params->dst.addr.buffer);
>
> For depth clears, you may not have a destination. Probably best to
> make this one conditional as well. Otherwise, we'll add NULL to the
> set.
>
> +
> /* Flush the sampler cache so any texturing from the destination
> is
> * coherent.
> */
> --
> 2.5.5
> _______________________________________________
> mesa-dev mailing list
> [3]mesa-dev@lists.freedesktop.org
> [4]https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
> References
>
> 1. mailto:topi.pohjolai...@gmail.com
> 2. mailto:topi.pohjolai...@intel.com
> 3. mailto:mesa-dev@lists.freedesktop.org
> 4. https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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