This number was chosen in an attempt to match the limits applied to
GLSL IR.
A recent attempt to disable the GLSL IR optimisation loop in the i965
backend resulted in 4 loops from The Talos Principle failing to unroll.
Bumping the limit allows them to unroll which results in the instruction
count matching the previous output from when the GLSL IR opts were still
enabled.
A look at the git history of the why these limits were chosen for GLSL IR
shows it was more to do with the slow speed of unrolling large loops in
GLSL IR than anything else. The speed of loop unrolling in NIR is not a
problem so we may wish to bump this even higher in future.
---
src/compiler/nir/nir_opt_loop_unroll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_opt_loop_unroll.c
b/src/compiler/nir/nir_opt_loop_unroll.c
index 2c19980..37cbced 100644
--- a/src/compiler/nir/nir_opt_loop_unroll.c
+++ b/src/compiler/nir/nir_opt_loop_unroll.c
@@ -460,7 +460,7 @@ is_loop_small_enough_to_unroll(nir_shader *shader,
nir_loop_info *li)
return true;
bool loop_not_too_large =
- li->num_instructions * li->trip_count <= max_iter * 25;
+ li->num_instructions * li->trip_count <= max_iter * 26;
return loop_not_too_large;
}
--
2.9.3
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