2016-12-02 21:39 GMT+01:00 Marek Olšák <mar...@gmail.com>:
> From: Marek Olšák <marek.ol...@amd.com>
>
> It really happens.
> ---
> src/gallium/drivers/radeonsi/si_descriptors.c | 1 +
> src/gallium/drivers/radeonsi/si_pipe.h | 3 +++
> src/gallium/drivers/radeonsi/si_state.c | 5 +++++
> 3 files changed, 9 insertions(+)
>
> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
> b/src/gallium/drivers/radeonsi/si_descriptors.c
> index 8b6e0bb..4f78b1a 100644
> --- a/src/gallium/drivers/radeonsi/si_descriptors.c
> +++ b/src/gallium/drivers/radeonsi/si_descriptors.c
> @@ -796,20 +796,21 @@ static void si_bind_sampler_states(struct
> pipe_context *ctx,
> if (!count || shader >= SI_NUM_SHADERS)
> return;
>
> for (i = 0; i < count; i++) {
> unsigned slot = start + i;
>
> if (!sstates[i] ||
> sstates[i] == samplers->views.sampler_states[slot])
> continue;
>
> + assert(sstates[i]->magic == SI_SAMPLER_STATE_MAGIC);
> samplers->views.sampler_states[slot] = sstates[i];
>
> /* If FMASK is bound, don't overwrite it.
> * The sampler state will be set after FMASK is unbound.
> */
> if (samplers->views.views[slot] &&
> samplers->views.views[slot]->texture &&
> samplers->views.views[slot]->texture->target !=
> PIPE_BUFFER &&
> ((struct r600_texture*)samplers->views.
> views[slot]->texture)->fmask.size)
> continue;
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/
> radeonsi/si_pipe.h
> index 42cbecb..a7985e7 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.h
> +++ b/src/gallium/drivers/radeonsi/si_pipe.h
> @@ -130,21 +130,24 @@ struct si_sampler_view {
> /* [0..7] = image descriptor
> * [4..7] = buffer descriptor */
> uint32_t state[8];
> uint32_t fmask_state[8];
> const struct radeon_surf_level *base_level_info;
> unsigned base_level;
> unsigned block_width;
> bool is_stencil_sampler;
> };
>
> +#define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
> +
> struct si_sampler_state {
> + unsigned magic;
>
How about wrapping it in #ifndef NDEBUG/#endif? Here and the other places.
> uint32_t val[4];
> };
>
> struct si_cs_shader_state {
> struct si_compute *program;
> struct si_compute *emitted_program;
> unsigned offset;
> bool initialized;
> bool uses_scratch;
> };
> diff --git a/src/gallium/drivers/radeonsi/si_state.c
> b/src/gallium/drivers/radeonsi/si_state.c
> index 1ccf5b6..7ff9f8c 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -3240,20 +3240,21 @@ static void *si_create_sampler_state(struct
> pipe_context *ctx,
> util_memcpy_cpu_to_le32(&sctx-
> >border_color_map[i],
>
> &state->border_color,
>
> sizeof(state->border_color));
> sctx->border_color_count++;
> }
>
> border_color_index = i;
> }
> }
>
> + rstate->magic = SI_SAMPLER_STATE_MAGIC;
> rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
> S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
> S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
> S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
> S_008F30_DEPTH_COMPARE_FUNC(
> si_tex_compare(state->compare_func)) |
>
> S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords)
> |
> S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
> S_008F30_ANISO_BIAS(max_aniso_ratio) |
>
> S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map)
> |
> S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
> @@ -3296,20 +3297,24 @@ static void si_emit_sample_mask(struct si_context
> *sctx, struct r600_atom *atom)
> assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
> (mask & 1 && sctx->blitter->running));
>
> radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0,
> 2);
> radeon_emit(cs, mask | (mask << 16));
> radeon_emit(cs, mask | (mask << 16));
> }
>
> static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
> {
> + struct si_sampler_state *s = state;
> +
> + assert(s->magic == SI_SAMPLER_STATE_MAGIC);
> + s->magic = 0;
> free(state);
> }
>
> /*
> * Vertex elements & buffers
> */
>
> static void *si_create_vertex_elements(struct pipe_context *ctx,
> unsigned count,
> const struct pipe_vertex_element
> *elements)
> --
> 2.7.4
>
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