From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeonsi/si_blit.c | 2 +-
src/gallium/drivers/radeonsi/si_descriptors.c | 4 ++--
src/gallium/drivers/radeonsi/si_state.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index f5f49c1..83870e5 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -71,21 +71,21 @@ static void si_blitter_begin(struct pipe_context *ctx, enum
si_blitter_op op)
util_blitter_save_viewport(sctx->blitter,
&sctx->b.viewports.states[0]);
util_blitter_save_scissor(sctx->blitter,
&sctx->b.scissors.states[0]);
}
if (op & SI_SAVE_FRAMEBUFFER)
util_blitter_save_framebuffer(sctx->blitter,
&sctx->framebuffer.state);
if (op & SI_SAVE_TEXTURES) {
util_blitter_save_fragment_sampler_states(
sctx->blitter, 2,
-
sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
+
(void**)sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
}
if (op & SI_DISABLE_RENDER_COND)
sctx->b.render_cond_force_off = true;
}
static void si_blitter_end(struct pipe_context *ctx)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index cf66102..8b6e0bb 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -449,39 +449,39 @@ static void si_set_sampler_view(struct si_context *sctx,
rtex->fmask.size) {
memcpy(desc + 8,
rview->fmask_state, 8*4);
} else {
/* Disable FMASK and bind sampler state in [12:15]. */
memcpy(desc + 8,
null_texture_descriptor, 4*4);
if (views->sampler_states[slot])
memcpy(desc + 12,
- views->sampler_states[slot], 4*4);
+ views->sampler_states[slot]->val, 4*4);
}
views->enabled_mask |= 1u << slot;
/* Since this can flush, it must be done after enabled_mask is
* updated. */
si_sampler_view_add_buffer(sctx, view->texture,
RADEON_USAGE_READ,
rview->is_stencil_sampler, true);
} else {
pipe_sampler_view_reference(&views->views[slot], NULL);
memcpy(desc, null_texture_descriptor, 8*4);
/* Only clear the lower dwords of FMASK. */
memcpy(desc + 8, null_texture_descriptor, 4*4);
/* Re-set the sampler state if we are transitioning from FMASK.
*/
if (views->sampler_states[slot])
memcpy(desc + 12,
- views->sampler_states[slot], 4*4);
+ views->sampler_states[slot]->val, 4*4);
views->enabled_mask &= ~(1u << slot);
}
descs->dirty_mask |= 1u << slot;
sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
}
static bool is_compressed_colortex(struct r600_texture *rtex)
{
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index 3a9f0cf..eb7a69f 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -238,21 +238,21 @@ struct si_descriptors {
/* The shader userdata offset within a shader where the 64-bit pointer
to the descriptor
* array will be stored. */
unsigned shader_userdata_offset;
/* Whether the pointer should be re-emitted. */
bool pointer_dirty;
};
struct si_sampler_views {
struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
- void *sampler_states[SI_NUM_SAMPLERS];
+ struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
/* The i-th bit is set if that element is enabled (non-NULL resource).
*/
unsigned enabled_mask;
};
struct si_buffer_resources {
enum radeon_bo_usage shader_usage; /* READ, WRITE, or
READWRITE */
enum radeon_bo_priority priority;
struct pipe_resource **buffers; /* this has num_buffers
elements */
--
2.7.4
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