[Mesa-dev] [PATCH v3 2/6] nv50/ir: implement mad post ra folding for nvc0+

[Karol Herbst]

changes for GpuTest /test=pixmark_piano /benchmark /no_scorebox /msaa=0
/benchmark_duration_ms=60000 /width=1024 /height=640:

score: 1026 -> 1044

changes for shader-db:

total instructions in shared programs : 3499445 -> 3491273 (-0.23%)
total gprs used in shared programs    : 453803 -> 453803 (0.00%)
total local used in shared programs   : 21621 -> 21621 (0.00%)
total bytes used in shared programs   : 32074936 -> 32000072 (-0.23%)

                local        gpr       inst      bytes
    helped           0           0        3503        3503
      hurt           0           0           0           0

v2: removed TODO
    reorderd to show changes without RA modification
    removed stale debugging print() call
v3: remove predicate checks
    enable only for gf100 ISA

Signed-off-by: Karol Herbst <karolher...@gmail.com>

fixup

Signed-off-by: Karol Herbst <karolher...@gmail.com>
---
 .../drivers/nouveau/codegen/nv50_ir_peephole.cpp   | 53 +++++++++++++++++++---
 1 file changed, 47 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 858f27f..6d5e662 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -3054,14 +3054,13 @@ FlatteningPass::tryPredicateConditional(BasicBlock *bb)
 
 // Fold Immediate into MAD; must be done after register allocation due to
 // constraint SDST == SSRC2
-// TODO:
-// Does NVC0+ have other situations where this pass makes sense?
 class PostRaConstantFolding : public Pass
 {
 private:
    virtual bool visit(Instruction *);
 
-   void handleMAD(Instruction *);
+   void handleMADforNV50(Instruction *);
+   void handleMADforNVC0(Instruction *);
 };
 
 static bool
@@ -3076,7 +3075,7 @@ post_ra_dead(Instruction *i)
 // Fold Immediate into MAD; must be done after register allocation due to
 // constraint SDST == SSRC2
 void
-PostRaConstantFolding::handleMAD(Instruction *i)
+PostRaConstantFolding::handleMADforNV50(Instruction *i)
 {
    if (i->def(0).getFile() != FILE_GPR ||
        i->src(0).getFile() != FILE_GPR ||
@@ -3129,12 +3128,54 @@ PostRaConstantFolding::handleMAD(Instruction *i)
    }
 }
 
+void
+PostRaConstantFolding::handleMADforNVC0(Instruction *i)
+{
+   if (i->def(0).getFile() != FILE_GPR ||
+       i->src(0).getFile() != FILE_GPR ||
+       i->src(1).getFile() != FILE_GPR ||
+       i->src(2).getFile() != FILE_GPR ||
+       i->getDef(0)->reg.data.id != i->getSrc(2)->reg.data.id)
+      return;
+
+   // TODO: gm107 can also do this for S32, maybe other chipsets as well
+   if (i->dType != TYPE_F32)
+      return;
+
+   if ((i->src(2).mod | Modifier(NV50_IR_MOD_NEG)) != 
Modifier(NV50_IR_MOD_NEG))
+      return;
+
+   ImmediateValue val;
+   int s;
+
+   if (i->src(0).getImmediate(val))
+      s = 1;
+   else if (i->src(1).getImmediate(val))
+      s = 0;
+   else
+      return;
+
+   if ((i->src(s).mod | Modifier(NV50_IR_MOD_NEG)) != 
Modifier(NV50_IR_MOD_NEG))
+      return;
+
+   if (s == 1)
+      i->swapSources(0, 1);
+
+   Instruction *imm = i->getSrc(1)->getInsn();
+   i->setSrc(1, imm->getSrc(0));
+   if (post_ra_dead(imm))
+      delete_Instruction(prog, imm);
+}
+
 bool
 PostRaConstantFolding::visit(Instruction *i)
 {
    switch (i->op) {
    case OP_MAD:
-      handleMAD(i);
+      if (prog->getTarget()->getChipset() < 0xc0)
+         handleMADforNV50(i);
+      else
+         handleMADforNVC0(i);
       break;
    default:
       break;
@@ -3558,7 +3599,7 @@ bool
 Program::optimizePostRA(int level)
 {
    RUN_PASS(2, FlatteningPass, run);
-   if (getTarget()->getChipset() < 0xc0)
+   if (getTarget()->getChipset() < NVISA_GK20A_CHIPSET)
       RUN_PASS(2, PostRaConstantFolding, run);
 
    return true;
-- 
2.10.1

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