---
src/intel/vulkan/anv_pipeline.c | 2 +-
src/mesa/drivers/dri/i965/brw_compiler.h | 1 +
src/mesa/drivers/dri/i965/brw_nir.c | 3 ++-
src/mesa/drivers/dri/i965/brw_nir.h | 2 +-
src/mesa/drivers/dri/i965/brw_vec4.cpp | 20 ++++++++++----------
src/mesa/drivers/dri/i965/brw_vs.c | 2 +-
6 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 0aac711..4e7a725 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -467,7 +467,7 @@ anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
unsigned code_size;
const unsigned *shader_code =
- brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir,
+ brw_compile_vs(compiler, NULL, mem_ctx, &key, &prog_data, nir->info,
nir,
NULL, false, -1, &code_size, NULL);
if (shader_code == NULL) {
ralloc_free(mem_ctx);
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h
b/src/mesa/drivers/dri/i965/brw_compiler.h
index 819c7d6..69ab68d 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.h
+++ b/src/mesa/drivers/dri/i965/brw_compiler.h
@@ -770,6 +770,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void
*log_data,
void *mem_ctx,
const struct brw_vs_prog_key *key,
struct brw_vs_prog_data *prog_data,
+ shader_info *info,
const struct nir_shader *shader,
gl_clip_plane *clip_planes,
bool use_legacy_snorm_formula,
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_nir.c
index a93d825..bc5a1a1 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -191,6 +191,7 @@ remap_patch_urb_offsets(nir_block *block, nir_builder *b,
void
brw_nir_lower_vs_inputs(nir_shader *nir,
+ shader_info *info,
bool is_scalar,
bool use_legacy_snorm_formula,
const uint8_t *vs_attrib_wa_flags)
@@ -220,7 +221,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
nir_foreach_function(function, nir) {
if (function->impl) {
nir_foreach_block(block, function->impl) {
- remap_vs_attrs(block, nir->info);
+ remap_vs_attrs(block, info);
}
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_nir.h
b/src/mesa/drivers/dri/i965/brw_nir.h
index 3c774d0..366d365 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.h
+++ b/src/mesa/drivers/dri/i965/brw_nir.h
@@ -97,7 +97,7 @@ nir_shader *brw_preprocess_nir(const struct brw_compiler
*compiler,
bool brw_nir_lower_intrinsics(nir_shader *nir,
struct brw_stage_prog_data *prog_data);
-void brw_nir_lower_vs_inputs(nir_shader *nir,
+void brw_nir_lower_vs_inputs(nir_shader *nir, shader_info *info,
bool is_scalar,
bool use_legacy_snorm_formula,
const uint8_t *vs_attrib_wa_flags);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index c93e2e5..1494980 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -2103,6 +2103,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void
*log_data,
void *mem_ctx,
const struct brw_vs_prog_key *key,
struct brw_vs_prog_data *prog_data,
+ shader_info *info,
const nir_shader *src_shader,
gl_clip_plane *clip_planes,
bool use_legacy_snorm_formula,
@@ -2114,7 +2115,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void
*log_data,
nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
shader = brw_nir_apply_sampler_key(shader, compiler->devinfo, &key->tex,
is_scalar);
- brw_nir_lower_vs_inputs(shader, is_scalar,
+ brw_nir_lower_vs_inputs(shader, info, is_scalar,
use_legacy_snorm_formula, key->gl_attrib_wa_flags);
brw_nir_lower_vue_outputs(shader, is_scalar);
shader = brw_postprocess_nir(shader, compiler->devinfo, is_scalar);
@@ -2126,7 +2127,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void
*log_data,
/* gl_VertexID and gl_InstanceID are system values, but arrive via an
* incoming vertex attribute. So, add an extra slot.
*/
- if (shader->info->system_values_read &
+ if (info->system_values_read &
(BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX) |
BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
@@ -2135,14 +2136,14 @@ brw_compile_vs(const struct brw_compiler *compiler,
void *log_data,
}
/* gl_DrawID has its very own vec4 */
- if (shader->info->system_values_read &
+ if (info->system_values_read &
BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID)) {
nr_attributes++;
}
unsigned nr_attribute_slots =
nr_attributes +
- _mesa_bitcount_64(shader->info->double_inputs_read);
+ _mesa_bitcount_64(info->double_inputs_read);
/* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
* Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
@@ -2175,7 +2176,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void
*log_data,
fs_visitor v(compiler, log_data, mem_ctx, key, &prog_data->base.base,
NULL, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
- shader, shader->info, 8, shader_time_index);
+ shader, info, 8, shader_time_index);
if (!v.run_vs(clip_planes)) {
if (error_str)
*error_str = ralloc_strdup(mem_ctx, v.fail_msg);
@@ -2191,9 +2192,8 @@ brw_compile_vs(const struct brw_compiler *compiler, void
*log_data,
if (INTEL_DEBUG & DEBUG_VS) {
const char *debug_name =
ralloc_asprintf(mem_ctx, "%s vertex shader %s",
- shader->info->label ? shader->info->label :
- "unnamed",
- shader->info->name);
+ info->label ? info->label : "unnamed",
+ info->name);
g.enable_debug(debug_name);
}
@@ -2205,7 +2205,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void
*log_data,
prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
vec4_vs_visitor v(compiler, log_data, key, prog_data,
- shader, shader->info, clip_planes, mem_ctx,
+ shader, info, clip_planes, mem_ctx,
shader_time_index, use_legacy_snorm_formula);
if (!v.run()) {
if (error_str)
@@ -2215,7 +2215,7 @@ brw_compile_vs(const struct brw_compiler *compiler, void
*log_data,
}
assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx,
- shader, shader->info,
&prog_data->base,
+ shader, info, &prog_data->base,
v.cfg, final_assembly_size);
}
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
b/src/mesa/drivers/dri/i965/brw_vs.c
index b5111d8..eb878ca 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -191,7 +191,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
*/
char *error_str;
program = brw_compile_vs(compiler, brw, mem_ctx, key, &prog_data,
- vp->program.nir,
+ &vp->program.info, vp->program.nir,
brw_select_clip_planes(&brw->ctx),
!_mesa_is_gles3(&brw->ctx),
st_index, &program_size, &error_str);
--
2.5.0.400.gff86faf
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