On Tue, Sep 6, 2016 at 12:28 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:
> Once mcs buffer gets allocated without delay for lossless
> compression (same as we do for msaa), one gets regression in:
>
> GL45-CTS.texture_barrier_ARB.same-texel-rw
>
> Setting the auxiliary surface for both sampling engine and data
> port seems to fix this. I haven't found any hardware documentation
> backing this though.
>
> v2 (Jason): Prepare also for the case where surface is sampled with
> non-compressible format forcing also rendering without
> compression.
>
> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 74
> +++++++++++++++++++++++-
> 1 file changed, 71 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index af102a9..05b214f 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -77,6 +77,76 @@ static const struct surface_state_info
> surface_state_infos[] = {
> [9] = {16, 64, 8, 10, SKL_MOCS_WB, SKL_MOCS_PTE},
> };
>
> +static unsigned
> +brw_find_matching_rb(const struct gl_framebuffer *fb,
> + const struct intel_mipmap_tree *mt)
> +{
> + for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
> + const struct intel_renderbuffer *irb =
> + intel_renderbuffer(fb->_ColorDrawBuffers[i]);
> +
> + if (irb->mt == mt)
> + return i;
> + }
> +
> + return fb->_NumColorDrawBuffers;
> +}
> +
> +static bool
> +brw_needs_aux_surface(const struct brw_context *brw,
> + const struct intel_mipmap_tree *mt, int flags,
> + const struct isl_view *view)
> +{
> + if (!mt->mcs_mt)
> + return false;
> +
> + if (view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT &&
> + !(flags & INTEL_RENDERBUFFER_AUX_DISABLED))
> + return true;
> +
> + const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;
> + const bool is_lossless_compressed =
> + intel_miptree_is_lossless_compressed(brw, mt);
> + const bool view_format_lossless_compressed =
> + isl_format_supports_lossless_compression(brw->intelScreen->
> devinfo,
> + view->format);
> + const unsigned rb_index = brw_find_matching_rb(fb, mt);
> +
> + /* If the underlying surface is compressed but it is sampled using a
> + * format that the sampling engine doesn't support as compressed, there
> + * is no alternative but to treat the surface as non-compressed.
> + */
> + if (is_lossless_compressed && !view_format_lossless_compressed) {
> + /* Logic elsewhere needs to take care to resolve the color buffer
> prior
> + * to sampling it as non-compressed.
> + */
> + assert(mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED);
> +
> + /* In practise it looks that setting the same lossless compressed
> + * surface to be sampled without auxiliary surface and to be written
> + * with auxiliary surface confuses the hardware. Therefore any
> + * corresponding renderbuffer must be set up with auxiliary buffer
> + * disabled.
> + */
> + assert(rb_index == fb->_NumColorDrawBuffers ||
> + brw->draw_aux_buffer_disabled[rb_index]);
> + return false;
> + }
> +
> + /* In practise it looks that setting the same lossless compressed
> surface
> + * to be sampled without auxiliary surface and to be written with
> auxiliary
> + * surface confuses the hardware. Therefore sampler engine must be
> provided
> + * with auxiliary buffer regardless of the fast clear state if the same
> + * surface is also going to be written during the same rendering pass.
> + */
> + if (is_lossless_compressed && rb_index < fb->_NumColorDrawBuffers) {
> + assert(!brw->draw_aux_buffer_disabled[rb_index]);
> + return true;
> + }
> +
> + return mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED;]
>
How much of this really belongs in emit_surface_state? It seems like we
ought to have someone else make those decisions and simply pass us the
AUX_DISABLED bit.
> +}
> +
> static void
> brw_emit_surface_state(struct brw_context *brw,
> struct intel_mipmap_tree *mt, int flags,
> @@ -140,9 +210,7 @@ brw_emit_surface_state(struct brw_context *brw,
> struct isl_surf *aux_surf = NULL, aux_surf_s;
> uint64_t aux_offset = 0;
> enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;
> - if (mt->mcs_mt &&
> - ((view.usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) ||
> - mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED)) {
> + if (brw_needs_aux_surface(brw, mt, flags, &view)) {
> intel_miptree_get_aux_isl_surf(brw, mt, &aux_surf_s, &aux_usage);
> aux_surf = &aux_surf_s;
> assert(mt->mcs_mt->offset == 0);
> --
> 2.5.5
>
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