---
src/mesa/drivers/dri/i965/blorp.c | 3 +--
src/mesa/drivers/dri/i965/blorp.h | 20 ++++++++++++++++++--
src/mesa/drivers/dri/i965/blorp_priv.h | 2 +-
src/mesa/drivers/dri/i965/brw_blorp.c | 12 ++++++------
src/mesa/drivers/dri/i965/brw_blorp.h | 2 +-
src/mesa/drivers/dri/i965/brw_clear.c | 4 ++--
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/gen8_depth_state.c | 12 ++++++------
src/mesa/drivers/dri/i965/genX_blorp_exec.h | 18 +++++++++---------
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 18 +++++++++---------
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
src/mesa/drivers/dri/i965/intel_resolve_map.c | 2 +-
src/mesa/drivers/dri/i965/intel_resolve_map.h | 22 +++-------------------
13 files changed, 59 insertions(+), 60 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/blorp.c
b/src/mesa/drivers/dri/i965/blorp.c
index ada17ad..7b2fc7f 100644
--- a/src/mesa/drivers/dri/i965/blorp.c
+++ b/src/mesa/drivers/dri/i965/blorp.c
@@ -142,7 +142,6 @@ void
brw_blorp_params_init(struct brw_blorp_params *params)
{
memset(params, 0, sizeof(*params));
- params->hiz_op = GEN6_HIZ_OP_NONE;
params->num_draw_buffers = 1;
params->num_layers = 1;
}
@@ -347,7 +346,7 @@ brw_blorp_compile_nir_shader(struct blorp_context *blorp,
struct nir_shader *nir
void
blorp_gen6_hiz_op(struct blorp_context *blorp, void *batch,
struct brw_blorp_surf *surf, unsigned level, unsigned layer,
- enum gen6_hiz_op op)
+ enum blorp_hiz_op op)
{
struct brw_blorp_params params;
brw_blorp_params_init(¶ms);
diff --git a/src/mesa/drivers/dri/i965/blorp.h
b/src/mesa/drivers/dri/i965/blorp.h
index 9fb0c6e..b3217d0 100644
--- a/src/mesa/drivers/dri/i965/blorp.h
+++ b/src/mesa/drivers/dri/i965/blorp.h
@@ -28,7 +28,6 @@
#include "c11/threads.h"
#include "isl/isl.h"
-#include "intel_resolve_map.h" /* needed for enum gen6_hiz_op */
struct brw_context;
struct brw_wm_prog_key;
@@ -118,10 +117,27 @@ void
brw_blorp_ccs_resolve(struct blorp_context *blorp, void *batch,
struct brw_blorp_surf *surf, enum isl_format format);
+/**
+ * For an overview of the HiZ operations, see the following sections of the
+ * Sandy Bridge PRM, Volume 1, Part2:
+ * - 7.5.3.1 Depth Buffer Clear
+ * - 7.5.3.2 Depth Buffer Resolve
+ * - 7.5.3.3 Hierarchical Depth Buffer Resolve
+ *
+ * Of these, two get entered in the resolve map as needing to be done to the
+ * buffer: depth resolve and hiz resolve.
+ */
+enum blorp_hiz_op {
+ BLORP_HIZ_OP_NONE,
+ BLORP_HIZ_OP_DEPTH_CLEAR,
+ BLORP_HIZ_OP_DEPTH_RESOLVE,
+ BLORP_HIZ_OP_HIZ_RESOLVE,
+};
+
void
blorp_gen6_hiz_op(struct blorp_context *blorp, void *batch,
struct brw_blorp_surf *surf, unsigned level, unsigned layer,
- enum gen6_hiz_op op);
+ enum blorp_hiz_op op);
#ifdef __cplusplus
} /* end extern "C" */
diff --git a/src/mesa/drivers/dri/i965/blorp_priv.h
b/src/mesa/drivers/dri/i965/blorp_priv.h
index b823c77..6aa20b2 100644
--- a/src/mesa/drivers/dri/i965/blorp_priv.h
+++ b/src/mesa/drivers/dri/i965/blorp_priv.h
@@ -174,7 +174,7 @@ struct brw_blorp_params
uint32_t depth_format;
struct brw_blorp_surface_info src;
struct brw_blorp_surface_info dst;
- enum gen6_hiz_op hiz_op;
+ enum blorp_hiz_op hiz_op;
enum blorp_fast_clear_op fast_clear_op;
bool color_write_disable[4];
struct brw_blorp_wm_inputs wm_inputs;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 9a9e49d..74f74c5 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -834,7 +834,7 @@ brw_blorp_resolve_color(struct brw_context *brw, struct
intel_mipmap_tree *mt)
static void
gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
- unsigned int level, unsigned int layer, enum gen6_hiz_op
op)
+ unsigned int level, unsigned int layer, enum blorp_hiz_op
op)
{
intel_miptree_check_level_layer(mt, level, layer);
intel_miptree_used_for_rendering(mt);
@@ -859,21 +859,21 @@ gen6_blorp_hiz_exec(struct brw_context *brw, struct
intel_mipmap_tree *mt,
*/
void
intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
- unsigned int level, unsigned int layer, enum gen6_hiz_op op)
+ unsigned int level, unsigned int layer, enum blorp_hiz_op op)
{
const char *opname = NULL;
switch (op) {
- case GEN6_HIZ_OP_DEPTH_RESOLVE:
+ case BLORP_HIZ_OP_DEPTH_RESOLVE:
opname = "depth resolve";
break;
- case GEN6_HIZ_OP_HIZ_RESOLVE:
+ case BLORP_HIZ_OP_HIZ_RESOLVE:
opname = "hiz ambiguate";
break;
- case GEN6_HIZ_OP_DEPTH_CLEAR:
+ case BLORP_HIZ_OP_DEPTH_CLEAR:
opname = "depth clear";
break;
- case GEN6_HIZ_OP_NONE:
+ case BLORP_HIZ_OP_NONE:
opname = "noop?";
break;
}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 94de307..9c71410 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -58,7 +58,7 @@ brw_blorp_resolve_color(struct brw_context *brw,
void
intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
- unsigned int level, unsigned int layer, enum gen6_hiz_op op);
+ unsigned int level, unsigned int layer, enum blorp_hiz_op op);
#ifdef __cplusplus
} /* extern "C" */
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index 1dfff09..cd2350c 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -187,11 +187,11 @@ brw_fast_clear_depth(struct gl_context *ctx)
for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
intel_hiz_exec(brw, mt, depth_irb->mt_level,
depth_irb->mt_layer + layer,
- GEN6_HIZ_OP_DEPTH_CLEAR);
+ BLORP_HIZ_OP_DEPTH_CLEAR);
}
} else {
intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer,
- GEN6_HIZ_OP_DEPTH_CLEAR);
+ BLORP_HIZ_OP_DEPTH_CLEAR);
}
if (brw->gen == 6) {
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index c36a539..b29933a 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1848,7 +1848,7 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
uint32_t tile_x, uint32_t tile_y);
void gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
- unsigned int level, unsigned int layer, enum gen6_hiz_op
op);
+ unsigned int level, unsigned int layer, enum blorp_hiz_op
op);
uint32_t get_hw_prim_for_gl_prim(int mode);
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index a780da6..4930991 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -398,9 +398,9 @@ const struct brw_tracked_state gen8_pma_fix = {
*/
void
gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
- unsigned int level, unsigned int layer, enum gen6_hiz_op op)
+ unsigned int level, unsigned int layer, enum blorp_hiz_op op)
{
- if (op == GEN6_HIZ_OP_NONE)
+ if (op == BLORP_HIZ_OP_NONE)
return;
/* Disable the PMA stall fix since we're about to do a HiZ operation. */
@@ -468,16 +468,16 @@ gen8_hiz_exec(struct brw_context *brw, struct
intel_mipmap_tree *mt,
uint32_t dw1 = 0;
switch (op) {
- case GEN6_HIZ_OP_DEPTH_RESOLVE:
+ case BLORP_HIZ_OP_DEPTH_RESOLVE:
dw1 |= GEN8_WM_HZ_DEPTH_RESOLVE;
break;
- case GEN6_HIZ_OP_HIZ_RESOLVE:
+ case BLORP_HIZ_OP_HIZ_RESOLVE:
dw1 |= GEN8_WM_HZ_HIZ_RESOLVE;
break;
- case GEN6_HIZ_OP_DEPTH_CLEAR:
+ case BLORP_HIZ_OP_DEPTH_CLEAR:
dw1 |= GEN8_WM_HZ_DEPTH_CLEAR;
break;
- case GEN6_HIZ_OP_NONE:
+ case BLORP_HIZ_OP_NONE:
unreachable("Should not get here.");
}
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.h
b/src/mesa/drivers/dri/i965/genX_blorp_exec.h
index fe6711f..f2c944b 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.h
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.h
@@ -533,16 +533,16 @@ blorp_emit_ps_config(struct blorp_batch batch,
blorp_emit(batch, GENX(3DSTATE_WM), wm) {
switch (params->hiz_op) {
- case GEN6_HIZ_OP_DEPTH_CLEAR:
+ case BLORP_HIZ_OP_DEPTH_CLEAR:
wm.DepthBufferClear = true;
break;
- case GEN6_HIZ_OP_DEPTH_RESOLVE:
+ case BLORP_HIZ_OP_DEPTH_RESOLVE:
wm.DepthBufferResolveEnable = true;
break;
- case GEN6_HIZ_OP_HIZ_RESOLVE:
+ case BLORP_HIZ_OP_HIZ_RESOLVE:
wm.HierarchicalDepthBufferResolveEnable = true;
break;
- case GEN6_HIZ_OP_NONE:
+ case BLORP_HIZ_OP_NONE:
break;
default:
unreachable("not reached");
@@ -616,16 +616,16 @@ blorp_emit_ps_config(struct blorp_batch batch,
wm.MaximumNumberofThreads = batch.blorp->isl_dev->info->max_wm_threads -
1;
switch (params->hiz_op) {
- case GEN6_HIZ_OP_DEPTH_CLEAR:
+ case BLORP_HIZ_OP_DEPTH_CLEAR:
wm.DepthBufferClear = true;
break;
- case GEN6_HIZ_OP_DEPTH_RESOLVE:
+ case BLORP_HIZ_OP_DEPTH_RESOLVE:
wm.DepthBufferResolveEnable = true;
break;
- case GEN6_HIZ_OP_HIZ_RESOLVE:
+ case BLORP_HIZ_OP_HIZ_RESOLVE:
wm.HierarchicalDepthBufferResolveEnable = true;
break;
- case GEN6_HIZ_OP_NONE:
+ case BLORP_HIZ_OP_NONE:
break;
default:
unreachable("not reached");
@@ -817,7 +817,7 @@ blorp_emit_depth_stencil_state(struct blorp_batch batch,
.DepthBufferWriteEnable = true,
};
- if (params->hiz_op == GEN6_HIZ_OP_DEPTH_RESOLVE) {
+ if (params->hiz_op == BLORP_HIZ_OP_DEPTH_RESOLVE) {
ds.DepthTestEnable = true;
ds.DepthTestFunction = COMPAREFUNCTION_NEVER;
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0836b92..8bd9932 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2001,7 +2001,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
exec_node_init(&m->link);
m->level = level;
m->layer = layer;
- m->need = GEN6_HIZ_OP_HIZ_RESOLVE;
+ m->need = BLORP_HIZ_OP_HIZ_RESOLVE;
exec_list_push_tail(&mt->hiz_map, &m->link);
}
@@ -2029,7 +2029,7 @@ intel_miptree_slice_set_needs_hiz_resolve(struct
intel_mipmap_tree *mt,
return;
intel_resolve_map_set(&mt->hiz_map,
- level, layer, GEN6_HIZ_OP_HIZ_RESOLVE);
+ level, layer, BLORP_HIZ_OP_HIZ_RESOLVE);
}
@@ -2042,7 +2042,7 @@ intel_miptree_slice_set_needs_depth_resolve(struct
intel_mipmap_tree *mt,
return;
intel_resolve_map_set(&mt->hiz_map,
- level, layer, GEN6_HIZ_OP_DEPTH_RESOLVE);
+ level, layer, BLORP_HIZ_OP_DEPTH_RESOLVE);
}
void
@@ -2062,7 +2062,7 @@ intel_miptree_slice_resolve(struct brw_context *brw,
struct intel_mipmap_tree *mt,
uint32_t level,
uint32_t layer,
- enum gen6_hiz_op need)
+ enum blorp_hiz_op need)
{
intel_miptree_check_level_layer(mt, level, layer);
@@ -2084,7 +2084,7 @@ intel_miptree_slice_resolve_hiz(struct brw_context *brw,
uint32_t layer)
{
return intel_miptree_slice_resolve(brw, mt, level, layer,
- GEN6_HIZ_OP_HIZ_RESOLVE);
+ BLORP_HIZ_OP_HIZ_RESOLVE);
}
bool
@@ -2094,13 +2094,13 @@ intel_miptree_slice_resolve_depth(struct brw_context
*brw,
uint32_t layer)
{
return intel_miptree_slice_resolve(brw, mt, level, layer,
- GEN6_HIZ_OP_DEPTH_RESOLVE);
+ BLORP_HIZ_OP_DEPTH_RESOLVE);
}
static bool
intel_miptree_all_slices_resolve(struct brw_context *brw,
struct intel_mipmap_tree *mt,
- enum gen6_hiz_op need)
+ enum blorp_hiz_op need)
{
bool did_resolve = false;
@@ -2121,7 +2121,7 @@ intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw,
struct intel_mipmap_tree *mt)
{
return intel_miptree_all_slices_resolve(brw, mt,
- GEN6_HIZ_OP_HIZ_RESOLVE);
+ BLORP_HIZ_OP_HIZ_RESOLVE);
}
bool
@@ -2129,7 +2129,7 @@ intel_miptree_all_slices_resolve_depth(struct brw_context
*brw,
struct intel_mipmap_tree *mt)
{
return intel_miptree_all_slices_resolve(brw, mt,
- GEN6_HIZ_OP_DEPTH_RESOLVE);
+ BLORP_HIZ_OP_DEPTH_RESOLVE);
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index c28fb33..bfe6968 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -999,7 +999,7 @@ intel_miptree_unmap(struct brw_context *brw,
void
intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
- unsigned int level, unsigned int layer, enum gen6_hiz_op op);
+ unsigned int level, unsigned int layer, enum blorp_hiz_op op);
#ifdef __cplusplus
}
diff --git a/src/mesa/drivers/dri/i965/intel_resolve_map.c
b/src/mesa/drivers/dri/i965/intel_resolve_map.c
index 3df4b88..26eac8b 100644
--- a/src/mesa/drivers/dri/i965/intel_resolve_map.c
+++ b/src/mesa/drivers/dri/i965/intel_resolve_map.c
@@ -35,7 +35,7 @@ void
intel_resolve_map_set(struct exec_list *resolve_map,
uint32_t level,
uint32_t layer,
- enum gen6_hiz_op need)
+ enum blorp_hiz_op need)
{
foreach_list_typed(struct intel_resolve_map, map, link, resolve_map) {
if (map->level == level && map->layer == layer) {
diff --git a/src/mesa/drivers/dri/i965/intel_resolve_map.h
b/src/mesa/drivers/dri/i965/intel_resolve_map.h
index 726b287..672a4aa 100644
--- a/src/mesa/drivers/dri/i965/intel_resolve_map.h
+++ b/src/mesa/drivers/dri/i965/intel_resolve_map.h
@@ -24,6 +24,7 @@
#pragma once
#include <stdint.h>
+#include "blorp.h"
#include "compiler/glsl/list.h"
#ifdef __cplusplus
@@ -31,23 +32,6 @@ extern "C" {
#endif
/**
- * For an overview of the HiZ operations, see the following sections of the
- * Sandy Bridge PRM, Volume 1, Part2:
- * - 7.5.3.1 Depth Buffer Clear
- * - 7.5.3.2 Depth Buffer Resolve
- * - 7.5.3.3 Hierarchical Depth Buffer Resolve
- *
- * Of these, two get entered in the resolve map as needing to be done to the
- * buffer: depth resolve and hiz resolve.
- */
-enum gen6_hiz_op {
- GEN6_HIZ_OP_DEPTH_CLEAR,
- GEN6_HIZ_OP_DEPTH_RESOLVE,
- GEN6_HIZ_OP_HIZ_RESOLVE,
- GEN6_HIZ_OP_NONE,
-};
-
-/**
* \brief Map of miptree slices to needed resolves.
*
* The map is implemented as a linear doubly-linked list.
@@ -78,14 +62,14 @@ struct intel_resolve_map {
uint32_t level;
uint32_t layer;
- enum gen6_hiz_op need;
+ enum blorp_hiz_op need;
};
void
intel_resolve_map_set(struct exec_list *resolve_map,
uint32_t level,
uint32_t layer,
- enum gen6_hiz_op need);
+ enum blorp_hiz_op need);
struct intel_resolve_map *
intel_resolve_map_get(struct exec_list *resolve_map,
--
2.5.0.400.gff86faf
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