From: Marek Olšák <marek.ol...@amd.com>
and rename the enum
---
src/gallium/drivers/r600/evergreen_state.c | 4 ++--
src/gallium/drivers/r600/r600_state.c | 4 ++--
src/gallium/drivers/radeon/radeon_winsys.h | 2 +-
src/gallium/drivers/radeonsi/si_debug.c | 2 +-
src/gallium/drivers/radeonsi/si_descriptors.c | 2 +-
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 463dc15..7611520 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2273,31 +2273,31 @@ static void evergreen_emit_gs_rings(struct r600_context
*rctx, struct r600_atom
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
if (state->enable) {
rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE,
rbuffer->gpu_address >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
-
RADEON_PRIO_RINGS_STREAMOUT));
+
RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
state->esgs_ring.buffer_size >> 8);
rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE,
rbuffer->gpu_address >> 8);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
-
RADEON_PRIO_RINGS_STREAMOUT));
+
RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
state->gsvs_ring.buffer_size >> 8);
} else {
radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
}
radeon_set_config_reg(cs, R_008040_WAIT_UNTIL,
S_008040_WAIT_3D_IDLE(1));
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 5b47089..046573f 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1956,30 +1956,30 @@ static void r600_emit_gs_rings(struct r600_context
*rctx, struct r600_atom *a)
radeon_set_config_reg(cs, R_008040_WAIT_UNTIL,
S_008040_WAIT_3D_IDLE(1));
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
if (state->enable) {
rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
-
RADEON_PRIO_RINGS_STREAMOUT));
+
RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
state->esgs_ring.buffer_size >> 8);
rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b,
&rctx->b.gfx, rbuffer,
RADEON_USAGE_READWRITE,
-
RADEON_PRIO_RINGS_STREAMOUT));
+
RADEON_PRIO_SHADER_RINGS));
radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
state->gsvs_ring.buffer_size >> 8);
} else {
radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
}
radeon_set_config_reg(cs, R_008040_WAIT_UNTIL,
S_008040_WAIT_3D_IDLE(1));
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index 72ba830..e4d669f 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -193,40 +193,40 @@ enum radeon_bo_priority {
/* gap: 20 */
RADEON_PRIO_CONST_BUFFER = 24,
RADEON_PRIO_DESCRIPTORS,
RADEON_PRIO_BORDER_COLORS,
RADEON_PRIO_SAMPLER_BUFFER = 28,
RADEON_PRIO_VERTEX_BUFFER,
RADEON_PRIO_SHADER_RW_BUFFER = 32,
- RADEON_PRIO_RINGS_STREAMOUT,
RADEON_PRIO_SCRATCH_BUFFER,
RADEON_PRIO_COMPUTE_GLOBAL,
RADEON_PRIO_SAMPLER_TEXTURE = 36,
RADEON_PRIO_SHADER_RW_IMAGE,
RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 40,
RADEON_PRIO_COLOR_BUFFER = 44,
RADEON_PRIO_DEPTH_BUFFER = 48,
RADEON_PRIO_COLOR_BUFFER_MSAA = 52,
RADEON_PRIO_DEPTH_BUFFER_MSAA = 56,
RADEON_PRIO_CMASK = 60,
RADEON_PRIO_DCC,
RADEON_PRIO_HTILE,
+ RADEON_PRIO_SHADER_RINGS,
/* 63 is the maximum value */
};
struct winsys_handle;
struct radeon_winsys_ctx;
struct radeon_winsys_cs_chunk {
unsigned cdw; /* Number of used dwords. */
unsigned max_dw; /* Maximum number of dwords. */
uint32_t *buf; /* The base pointer of the chunk. */
diff --git a/src/gallium/drivers/radeonsi/si_debug.c
b/src/gallium/drivers/radeonsi/si_debug.c
index ae11b2c..be300ac 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -554,33 +554,33 @@ static const char *priority_to_string(enum
radeon_bo_priority priority)
ITEM(SDMA_BUFFER),
ITEM(SDMA_TEXTURE),
ITEM(USER_SHADER),
ITEM(INTERNAL_SHADER),
ITEM(CONST_BUFFER),
ITEM(DESCRIPTORS),
ITEM(BORDER_COLORS),
ITEM(SAMPLER_BUFFER),
ITEM(VERTEX_BUFFER),
ITEM(SHADER_RW_BUFFER),
- ITEM(RINGS_STREAMOUT),
ITEM(SCRATCH_BUFFER),
ITEM(COMPUTE_GLOBAL),
ITEM(SAMPLER_TEXTURE),
ITEM(SHADER_RW_IMAGE),
ITEM(SAMPLER_TEXTURE_MSAA),
ITEM(COLOR_BUFFER),
ITEM(DEPTH_BUFFER),
ITEM(COLOR_BUFFER_MSAA),
ITEM(DEPTH_BUFFER_MSAA),
ITEM(CMASK),
ITEM(DCC),
ITEM(HTILE),
+ ITEM(SHADER_RINGS),
};
#undef ITEM
assert(priority < ARRAY_SIZE(table));
return table[priority];
}
static int bo_list_compare_va(const struct radeon_bo_list_item *a,
const struct radeon_bo_list_item *b)
{
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index fcc8a32..f03a895 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1765,21 +1765,21 @@ void si_init_all_descriptors(struct si_context *sctx)
null_texture_descriptor, &ce_offset);
si_init_descriptors(si_image_descriptors(sctx, i),
SI_SGPR_IMAGES, 8, SI_NUM_IMAGES,
null_image_descriptor, &ce_offset);
}
si_init_buffer_resources(&sctx->rw_buffers,
&sctx->descriptors[SI_DESCS_RW_BUFFERS],
SI_NUM_RW_BUFFERS, SI_SGPR_RW_BUFFERS,
- RADEON_USAGE_READWRITE,
RADEON_PRIO_RINGS_STREAMOUT,
+ RADEON_USAGE_READWRITE,
RADEON_PRIO_SHADER_RINGS,
&ce_offset);
si_init_descriptors(&sctx->vertex_buffers, SI_SGPR_VERTEX_BUFFERS,
4, SI_NUM_VERTEX_BUFFERS, NULL, NULL);
sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS);
assert(ce_offset <= 32768);
/* Set pipe_context functions. */
sctx->b.b.bind_sampler_states = si_bind_sampler_states;
--
2.7.4
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