From: Marek Olšák <marek.ol...@amd.com>
---
src/gallium/drivers/radeon/r600_streamout.c | 4 ++--
src/gallium/drivers/radeonsi/si_descriptors.c | 6 ++++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_streamout.c
b/src/gallium/drivers/radeon/r600_streamout.c
index 705eb13..b5296aa 100644
--- a/src/gallium/drivers/radeon/r600_streamout.c
+++ b/src/gallium/drivers/radeon/r600_streamout.c
@@ -211,31 +211,31 @@ static void r600_emit_streamout_begin(struct
r600_common_context *rctx, struct r
update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
radeon_set_context_reg_seq(cs,
R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 3);
radeon_emit(cs, (t[i]->b.buffer_offset +
t[i]->b.buffer_size) >> 2); /*
BUFFER_SIZE (in DW) */
radeon_emit(cs, stride_in_dw[i]); /*
VTX_STRIDE (in DW) */
radeon_emit(cs, va >> 8); /*
BUFFER_BASE */
r600_emit_reloc(rctx, &rctx->gfx,
r600_resource(t[i]->b.buffer),
- RADEON_USAGE_WRITE,
RADEON_PRIO_RINGS_STREAMOUT);
+ RADEON_USAGE_WRITE,
RADEON_PRIO_SHADER_RW_BUFFER);
/* R7xx requires this packet after updating BUFFER_BASE.
* Without this, R7xx locks up. */
if (rctx->family >= CHIP_RS780 && rctx->family <=
CHIP_RV740) {
radeon_emit(cs, PKT3(PKT3_STRMOUT_BASE_UPDATE,
1, 0));
radeon_emit(cs, i);
radeon_emit(cs, va >> 8);
r600_emit_reloc(rctx, &rctx->gfx,
r600_resource(t[i]->b.buffer),
- RADEON_USAGE_WRITE,
RADEON_PRIO_RINGS_STREAMOUT);
+ RADEON_USAGE_WRITE,
RADEON_PRIO_SHADER_RW_BUFFER);
}
}
if (rctx->streamout.append_bitmask & (1 << i) &&
t[i]->buf_filled_size_valid) {
uint64_t va = t[i]->buf_filled_size->gpu_address +
t[i]->buf_filled_size_offset;
/* Append. */
radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 1d04a9c..fcc8a32 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1304,21 +1304,22 @@ static void si_set_streamout_targets(struct
pipe_context *ctx,
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
/* Set the resource. */
pipe_resource_reference(&buffers->buffers[bufidx],
buffer);
radeon_add_to_buffer_list_check_mem(&sctx->b,
&sctx->b.gfx,
(struct
r600_resource*)buffer,
buffers->shader_usage,
- buffers->priority,
true);
+
RADEON_PRIO_SHADER_RW_BUFFER,
+ true);
buffers->enabled_mask |= 1u << bufidx;
} else {
/* Clear the descriptor and unset the resource. */
memset(descs->list + bufidx*4, 0,
sizeof(uint32_t) * 4);
pipe_resource_reference(&buffers->buffers[bufidx],
NULL);
buffers->enabled_mask &= ~(1u << bufidx);
}
descs->dirty_mask |= 1u << bufidx;
@@ -1467,21 +1468,22 @@ static void si_invalidate_buffer(struct pipe_context
*ctx, struct pipe_resource
if (buffers->buffers[i] != buf)
continue;
si_desc_reset_buffer_offset(ctx, descs->list + i*4,
old_va, buf);
descs->dirty_mask |= 1u << i;
sctx->descriptors_dirty |= 1u << SI_DESCS_RW_BUFFERS;
radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
rbuffer,
buffers->shader_usage,
- buffers->priority, true);
+
RADEON_PRIO_SHADER_RW_BUFFER,
+ true);
/* Update the streamout state. */
if (sctx->b.streamout.begin_emitted)
r600_emit_streamout_end(&sctx->b);
sctx->b.streamout.append_bitmask =
sctx->b.streamout.enabled_mask;
r600_streamout_buffers_dirty(&sctx->b);
}
/* Constant and shader buffers. */
--
2.7.4
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