On Thu, Jul 28, 2016 at 04:50:10PM +0300, Pohjolainen, Topi wrote:
> On Tue, Jul 26, 2016 at 03:11:07PM -0700, Jason Ekstrand wrote:
> > At one point, we were doing this correctly. It must have gotten lost in
> > one of the many rebases.
> > ---
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +++++-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > index 1911eef..330291c 100644
> > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > @@ -3208,6 +3208,9 @@ intel_miptree_get_aux_isl_surf(struct brw_context
> > *brw,
> > return;
> > }
> >
> > + /* Start with a copy of the original surface. */
> > + intel_miptree_get_isl_surf(brw, mt, surf);
>
> I don't understand why this is needed here. Just in the beginning of this
> function 'surf' is set against the mcs_mt (calls
> intel_miptree_get_isl_surf(brw, mt->mcs_mt, surf)).
It looks that patch five needs this when aux surfaces are initialised against
the main surface.
>
> > +
> > /* Figure out the format and tiling of the auxiliary surface */
> > switch (*usage) {
> > case ISL_AUX_USAGE_NONE:
> > @@ -3294,7 +3297,8 @@ intel_miptree_get_aux_isl_surf(struct brw_context
> > *brw,
> > * in elements of the primary color surface so we have to divide by the
> > * compression block height.
> > */
> > - surf->array_pitch_el_rows = mt->qpitch /
> > isl_format_get_layout(surf->format)->bh;
> > + surf->array_pitch_el_rows =
> > + mt->mcs_mt->qpitch / isl_format_get_layout(surf->format)->bh;
> > }
> >
> > union isl_color_value
> > --
> > 2.5.0.400.gff86faf
> >
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