This is designed to map the GLSL intrinsics. Should one have a desire to also support d3d11, one could figure out what the overlap is and rejigger the arguments so that both sets of desires are expressible. I glanced at SM5 sync before doing this, and TBH I couldn't really make sense of it:
https://msdn.microsoft.com/en-us/library/windows/desktop/hh447241(v=vs.85).aspx If you can interpret it and make concrete recommendations for change, I'm happy to accommodate. On Tue, Jan 19, 2016 at 12:04 PM, Roland Scheidegger <srol...@vmware.com> wrote: > I am actually wondering how well that would work for d3d11. > d3d11 just has AllMemoryBarrier, DeviceMemoryBarrier plus > GroupMemoryBarrier - and for each of them also a "WithGroupSync" > version. Hmm. > > Roland > > Am 19.01.2016 um 03:30 schrieb Ilia Mirkin: >> Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu> >> Reviewed-by: Marek Olšák <marek.ol...@amd.com> (v1) >> >> v1 -> v2: add defines for the various bits >> --- >> src/gallium/auxiliary/tgsi/tgsi_info.c | 2 +- >> src/gallium/docs/source/tgsi.rst | 17 +++++++++++++++++ >> src/gallium/include/pipe/p_shader_tokens.h | 7 ++++++- >> 3 files changed, 24 insertions(+), 2 deletions(-) >> >> diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c >> b/src/gallium/auxiliary/tgsi/tgsi_info.c >> index b270dd7..46b296f 100644 >> --- a/src/gallium/auxiliary/tgsi/tgsi_info.c >> +++ b/src/gallium/auxiliary/tgsi/tgsi_info.c >> @@ -149,7 +149,7 @@ static const struct tgsi_opcode_info >> opcode_info[TGSI_OPCODE_LAST] = >> { 1, 2, 0, 0, 0, 0, 0, COMP, "FSGE", TGSI_OPCODE_FSGE }, >> { 1, 2, 0, 0, 0, 0, 0, COMP, "FSLT", TGSI_OPCODE_FSLT }, >> { 1, 2, 0, 0, 0, 0, 0, COMP, "FSNE", TGSI_OPCODE_FSNE }, >> - { 0, 1, 0, 0, 0, 0, 1, NONE, "", 112 }, /* removed */ >> + { 0, 1, 0, 0, 0, 0, 0, OTHR, "MEMBAR", TGSI_OPCODE_MEMBAR }, >> { 0, 1, 0, 0, 0, 0, 0, NONE, "CALLNZ", TGSI_OPCODE_CALLNZ }, >> { 0, 1, 0, 0, 0, 0, 0, NONE, "", 114 }, /* removed */ >> { 0, 1, 0, 0, 0, 0, 0, NONE, "BREAKC", TGSI_OPCODE_BREAKC }, >> diff --git a/src/gallium/docs/source/tgsi.rst >> b/src/gallium/docs/source/tgsi.rst >> index 7810a3e..489cbb0 100644 >> --- a/src/gallium/docs/source/tgsi.rst >> +++ b/src/gallium/docs/source/tgsi.rst >> @@ -2372,6 +2372,23 @@ programs. >> the program. Results are unspecified if any of the remaining >> threads terminates or never reaches an executed BARRIER instruction. >> >> +.. opcode:: MEMBAR - Memory barrier >> + >> + ``MEMBAR type`` >> + >> + This opcode waits for the completion of all memory accesses based on >> + the type passed in. The type is an immediate bitfield with the following >> + meaning: >> + >> + Bit 0: Shader storage buffers >> + Bit 1: Atomic buffers >> + Bit 2: Images >> + Bit 3: Shared memory >> + Bit 4: Thread group >> + >> + These may be passed in in any combination. An implementation is free to >> not >> + distinguish between these as it sees fit. However these map to all the >> + possibilities made available by GLSL. >> >> .. _atomopcodes: >> >> diff --git a/src/gallium/include/pipe/p_shader_tokens.h >> b/src/gallium/include/pipe/p_shader_tokens.h >> index f300207..6539017 100644 >> --- a/src/gallium/include/pipe/p_shader_tokens.h >> +++ b/src/gallium/include/pipe/p_shader_tokens.h >> @@ -420,7 +420,7 @@ struct tgsi_property_data { >> #define TGSI_OPCODE_FSLT 110 >> #define TGSI_OPCODE_FSNE 111 >> >> - /* gap */ >> +#define TGSI_OPCODE_MEMBAR 112 >> #define TGSI_OPCODE_CALLNZ 113 >> /* gap */ >> #define TGSI_OPCODE_BREAKC 115 >> @@ -744,6 +744,11 @@ struct tgsi_instruction_memory >> unsigned Padding : 29; >> }; >> >> +#define TGSI_MEMBAR_SHADER_BUFFER (1 << 0) >> +#define TGSI_MEMBAR_ATOMIC_BUFFER (1 << 1) >> +#define TGSI_MEMBAR_SHADER_IMAGE (1 << 2) >> +#define TGSI_MEMBAR_SHARED (1 << 3) >> +#define TGSI_MEMBAR_THREAD_GROUP (1 << 4) >> >> #ifdef __cplusplus >> } >> > _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
