On 01/03/2016 08:48 AM, Francisco Jerez wrote:
> The RS and hardware binding tables are only supported on the 3D
> pipeline and can lead to corruption if left enabled during a GPGPU
> workload. Disable it when switching to the GPGPU (or media) pipeline
> and re-enable it when switching back to the 3D pipeline.
Yep, this is the way it is.
Reviewed-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_binding_tables.c | 2 +-
> src/mesa/drivers/dri/i965/brw_misc_state.c | 38
> ++++++++++++++++++++++++++
> src/mesa/drivers/dri/i965/brw_state.h | 1 +
> 3 files changed, 40 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c
> b/src/mesa/drivers/dri/i965/brw_binding_tables.c
> index 80935cf..5c5aa0e 100644
> --- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
> +++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
> @@ -364,7 +364,7 @@ gen7_disable_hw_binding_tables(struct brw_context *brw)
> /**
> * Enable hardware binding tables and set up the binding table pool.
> */
> -static void
> +void
> gen7_enable_hw_binding_tables(struct brw_context *brw)
> {
> if (!brw->use_resource_streamer)
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
> b/src/mesa/drivers/dri/i965/brw_misc_state.c
> index 2263604..7e68838 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -868,6 +868,25 @@ brw_emit_select_pipeline(struct brw_context *brw, enum
> brw_pipeline pipeline)
> const uint32_t _3DSTATE_PIPELINE_SELECT =
> is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45;
>
> + if (brw->use_resource_streamer && pipeline != BRW_RENDER_PIPELINE) {
> + /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
> + * PIPELINE_SELECT [DevBWR+]":
> + *
> + * Project: HSW, BDW, CHV, SKL, BXT
> + *
> + * Hardware Binding Tables are only supported for 3D workloads.
> Resource
> + * streamer must be enabled only for 3D workloads. Resource streamer
> + * must be disabled for Media and GPGPU workloads.
> + */
> + BEGIN_BATCH(1);
> + OUT_BATCH(MI_RS_CONTROL | 0);
> + ADVANCE_BATCH();
> +
> + gen7_disable_hw_binding_tables(brw);
> +
> + /* XXX - Disable gather constant pool too when we start using it. */
> + }
> +
> if (brw->gen >= 8) {
> /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
> * PIPELINE_SELECT [DevBWR+]":
> @@ -959,6 +978,25 @@ brw_emit_select_pipeline(struct brw_context *brw, enum
> brw_pipeline pipeline)
> OUT_BATCH(0);
> ADVANCE_BATCH();
> }
> +
> + if (brw->use_resource_streamer && pipeline == BRW_RENDER_PIPELINE) {
> + /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
> + * PIPELINE_SELECT [DevBWR+]":
> + *
> + * Project: HSW, BDW, CHV, SKL, BXT
> + *
> + * Hardware Binding Tables are only supported for 3D workloads.
> Resource
> + * streamer must be enabled only for 3D workloads. Resource streamer
> + * must be disabled for Media and GPGPU workloads.
> + */
> + BEGIN_BATCH(1);
> + OUT_BATCH(MI_RS_CONTROL | 1);
> + ADVANCE_BATCH();
> +
> + gen7_enable_hw_binding_tables(brw);
> +
> + /* XXX - Re-enable gather constant pool here. */
> + }
> }
>
> /**
> diff --git a/src/mesa/drivers/dri/i965/brw_state.h
> b/src/mesa/drivers/dri/i965/brw_state.h
> index d29b997..7d61b7c 100644
> --- a/src/mesa/drivers/dri/i965/brw_state.h
> +++ b/src/mesa/drivers/dri/i965/brw_state.h
> @@ -396,6 +396,7 @@ void gen7_update_binding_table_from_array(struct
> brw_context *brw,
> gl_shader_stage stage,
> const uint32_t* binding_table,
> int num_surfaces);
> +void gen7_enable_hw_binding_tables(struct brw_context *brw);
> void gen7_disable_hw_binding_tables(struct brw_context *brw);
> void gen7_reset_hw_bt_pool_offsets(struct brw_context *brw);
>
>
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