On Mon, 11 Apr 2011 17:16:34 +0800, "Zou, Nanhai" <nanhai....@intel.com> wrote: > In fact this is not zero at multi vs thread cases on GT1, it will trigger DP > read error when multi vs thread is enabled. > > I can not find where in spec says this payload M0.2 is reserved as zero,
g0.2 is delivered as 0. See vol2a.03: Thread Payload. We rely on that all over the place, not just in the VS. In brw_dp_read_4_vs, before your change, m0.2 was already getting set. In brw_dp_read_4_vs_relative, before your change, m0 was loaded with g0 through gen6_resolve_implied_move(p, &src, 0). In both cases, your change is dead instructions as far as I can see.
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